Modeling of a Magnetic Tunnel Junction for a Multilevel STT-MRAM Cell

Abstract

In the recent past, spin-transfer torque (STT) magnetic random access memories (MRAMs) have gained stupendous research interest with a potential to provide a solution for the on-chip memory applications. The prevailing single-level cell STT-MRAMs pose significant challenges due to scaling issues, making them unviable for the low-power and high-density embedded memory applications. This paper describes a pathway to design low-cost-per-bit, energy-efficient, and high-density multilevel cell (MLC) STT-MRAMs. This paper presents a model for magnetic tunnel junction (MTJ) devices based on in-plane magnetic anisotropy (IMA) and perpendicular magnetic anisotropy (PMA) using Verilog-A and elemental SPICE simulation framework. These MTJ devices are connected in series or parallel configuration to carry out a comparative performance analysis of series-MLC (sMLC) or parallel-MLC (pMLC) STT-MRAMs. The proposed model is validated using experimental results of IMA- and PMA-based sMLC and pMLC configurations, and the simulation results reveal a close agreement. The PMA-based pMLC configuration offers ultralow-voltage operation, least tunnel magnetoresistance degradations, and distinct presentation of resistance states, making it suitable for embedded memory applications.