Fabrication and Individual Addressing of STT-MRAM Bit Array With 50 nm Full Pitch

Abstract

Spin-transfer torque (STT) magnetic random access memory (MRAM) is gaining commercial traction in low-density embedded and standalone memories, but the available market opportunities would grow exponentially if STT-MRAM could approach dynamic random access memory (DRAM) bit density. Of course, achieving DRAM density will require, among other things, demonstrating the ability to pattern MRAM bits at an extremely tight pitch. Here, an experimental demonstration of fabrication and electrical testing of a STT-MRAM bit array are reported. By optimizing the hard mask and ion beam etching (IBE) processes, MRAM bit arrays with a full pitch down to 50 nm are fabricated, in which the bits are individually tested using a novel bottom-point-contact method.