Spin-transfer Torque Random Access Memory Research Articles

Overview of emerging nonvolatile memory technologies

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM

Spin-transfer torque random access memory (STT-RAM) is considered to be a leading candidate for next-generation memory. As technology scales, however, the sensing margin of STT-RAM is significantly degraded because of increased process variation. Furthermore, the sensing current should be <;20 μA to protect the read disturbance in the beyond 45-nm technology, leading to a further decrease in the sensing margin. To achieve a target yield of six sigma in the beyond 45-nm technology with a sensing current of <;20 μA, an offset-canceling triple-stage (OCTS) sensing circuit is proposed in this brief. The OCTS sensing circuit can overcome the sensing margin and read disturbance problems by sacrificing the sensing time. Monte Carlo HSPICE simulation results using a 45-nm technology model show that the OCTS sensing circuit achieves a target yield of six sigma (96.74% for 32 Mb) with a sensing current of 20 μA and a sensing time of 6.4 ns.

STT-RAM Cache Hierarchy With Multiretention MTJ Designs

Spin-transfer torque random access memory (STT-RAM) is the most promising candidate to be universal memory due to its good scalability, zero standby power, and radiation hardness. Having a cell area only 1/9 to 1/3 that of SRAM, allows for a much larger cache with the same die footprint. Such reduction of cell size can significantly shrink the cache array size, leading to significant improvement of overall system performance and power consumption, especially in this multicore era where locality is crucial. However, deploying STT-RAM technology in L1 caches is challenging because write operations on STT-RAM are slow and power-consuming. In this paper, we propose a range of cache hierarchy designs implemented entirely using STT-RAM that deliver optimal power saving and performance. In particular, our designs use STT-RAM cells with various data retention times and write performances, made possible by novel magnetic tunneling junction designs. For L1 caches where speed is of utmost importance, we propose a scheme that uses fast STT-RAM cells with reduced data retention time coupled with a dynamic refresh scheme. In the dynamic refresh scheme, another emerging technology, memristor, is used as the counter to monitor the data retention of the low-retention STT-RAM, achieving a higher array area efficiency than an SRAM-based counter. For lower level caches with relatively larger cache capacities, we propose a design that has partitions of different retention characteristics, and a data migration scheme that moves data between these partitions. The experiments show that on the average, our proposed multiretention level STT-RAM cache reduces total energy by as much as 30%–74.2% compared to previous single retention level STT-RAM caches, while improving instruction per cycle performance for both two-level and three-level cache hierarchies.

Achieving perpendicular anisotropy in half-metallic Heusler alloys for spin device applications

Various full Heusler alloys are interfaced with MgO and the magnetic properties of the Heusler-MgO junctions are studied. Next to MgO, the cubic Heusler system distorts to a tetragonal one, thereby inducing an anisotropy. The half-metallicity and nature of anisotropy (in-plane or perpendicular) in the Heusler-MgO system is governed mostly by the interface Heusler layers. There is a trend that Mn-O bonding near the MgO-Heusler junction results in perpendicular anisotropy. The ability to remain half-metallic and have perpendicular anisotropy makes some of these alloys potential candidates as free-layers in Spin Transfer Torque Random Access Memory (STT-RAM) devices, particularly, Cr2MnAs-MgO system with MnAs interface layers and Co2MnSi-MgO system with Mn2 interface layers.

Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory

Improving the vulnerability to soft errors is one of the important design goals for future architecture design of Chip-MultiProcessors (CMPs). In this study, we explore the soft error characteristics of CMPs with 3D stacked NonVolatile Memory (NVM), in particular, the Spin-Transfer Torque Random Access Memory (STT-RAM), whose cells are immune to radiation-induced soft errors and do not have endurance problems. We use 3D stacking as an enabler for modular integration of STT-RAM memories with minimum disruption in the baseline processor design flow, while providing further interconnection and capacity advantages. We take an in-depth look at alternative replacement schemes to explore the soft error resilience benefits and design trade-offs of 3D stacked STT-RAM and capture the multivariable optimization challenges microprocessor architectures face. We propose a vulnerability metric, with respect to the instruction and data in the core pipeline and through the cache hierarchy, to present a comprehensive system evaluation with respect to reliability, performance, and power consumption for our CMP architectures. Our experimental results show that, for the average workload, replacing memories with an STT-RAM alternative significantly mitigates soft errors on-chip, improves the performance by 14.15%, and reduces power consumption by 13.44%.

The Prospect of STT-RAM Scaling From Readability Perspective

Due to its fast access time, high integration density, nonvolatility and good CMOS compatibility, Spin-transfer torque random access memory (STT-RAM) becomes one promising technology for the memory hierarchy of the next-generation computing systems. In recent years, tremendous efforts have been made to reduce the switching current of magnetic tunneling junction (MTJ) for write performance and energy improvement. However, the success of write current reduction makes the STT-RAM read stability issue more prominent during the scaling of STT-RAM: following the decrease in MTJ switching current, the read current must scale accordingly to keep the disturbance on the MTJ resistance state at a minimum level. If the MTJ resistance and/or TMR values do not increase proportionally, the effective sense margin of STT-RAM will degrade, leading to a higher sensing error rate. In this work, we quantitatively analyzed the impacts of existing MTJ scaling rule on the readability STT-RAM, including both read disturbance and sensing errors. We also presented the importance of selecting an optimal read current for maintaining the readability of STT-RAM under the current scaling trend.

Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory

Spin-transfer torque random access memory (STT-RAM) has demonstrated great potentials as a universal memory for its fast access speed, zero standby power, excellent scalability, and simplicity of cell structure. However, large process variations of both magnetic tunneling junction (MTJ) and CMOS process severely limit the yield of STT-RAM chips and prevent the massive production from happening. In this paper, we analyze and compare the impacts of process variations on various sensing schemes of STT-RAM design. On top of it, we propose a novel voltage-driven nondestructive self-reference sensing scheme to enhance the STT-RAM chip yield by significantly improving sense margin. Monte Carlo simulations of a 16-Kb STT-RAM array shows that our proposed scheme can achieve the same yield as the previous nondestructive self-reference sensing scheme while improving the sense margin by five times with the similar access performance and power.

STT-RAM Cell Design Considering CMOS and MTJ Temperature Dependence

In spin-transfer torque random access memory (STT-RAM), the temperature fluctuations can significantly affect the characteristics of both electrical and magnetic devices. In this paper, we analyze their temperature dependence and investigate the impacts of temperature fluctuations on read and write operations. For the regular STT-RAM design working under 300 to 375 K, the sense margin in read operation can degrade about 25% and the write speed reduces around 20%. Furthermore, heating the MTJ to its Curie temperature can dramatically reduce the switching time to subnanosecond. And the design feasibility and implication are discussed in the paper.

VOLTAGE DRIVEN NONDESTRUCTIVE SELF-REFERENCE SENSING FOR STT-RAM YIELD ENHANCEMENT

Spin-transfer torque random access memory (STT-RAM) has demonstrated great potentials as a universal memory for its fast access speed, zero standby power, excellent scalability and simplicity of cell structure. However, large process variations of both magnetic tunneling junction and CMOS process severely limit the yield of STT-RAM chips. In this paper, we propose a novel voltage-driven non-destructive self-reference sensing scheme (NDRS) to enhance the STT-RAM chip yield by significantly improving sense margin. Monte-Carlo simulations of a 16 Kb STT-RAM array shows that our proposed scheme can achieve the same yield as the previous NDRS scheme while improving the sense margin by 5 × with the similar access performance and power.

STT-RAM CELL DESIGN CONSIDERING MTJ ASYMMETRIC SWITCHING

As one promising candidate for next-generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, nonvolatility, and good CMOS process compatibility. In this paper, we address the asymmetry in the write operations of STT-RAM cells: the mean and the deviation of the write latency for the switching from low- to high-resistance state is much longer or larger than that of the opposite direction. Some special design concerns, e.g., the data-dependent write reliability, are raised by this observation. We systematically analyze the root reasons for the asymmetric switching of MTJs, including the thermal-induced statistical MTJ magnetization process, the asymmetric biasing condition of NMOS transistors, and the device variations of both NMOS and MTJ. Their impacts on STT-RAM write operations were also investigated. At last, we explore the design spaces of different STT-RAM cell structures by considering the asymmetry of write operations.

Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder

In this article, we propose a data storage system with the emerging nonvolatile memory technologies used for the implantable electrocardiography (ECG) recorder. The proposed storage system can record the digitalized real-time ECG waveforms continuously inside the implantable device and export the stored data to external reader periodically to obtain a long-term backup. Spin transfer torque random access memory (STT-RAM) and spintronic memristor are selected as the storage elements for their nonvolatility, high density, high reliability, low power consumption, good scalability, and CMOS technology compatibility. The new read and write schemes of STT-RAM and spintronic memristors are presented and optimized to fit the specific application scenario. The tradeoffs among data accuracy, chip area, and read/write energy for the different technologies are thoroughly analyzed and compared. Our simulation results show the configuration with a data sampling rate (e.g., 128 Hz) and a quantization resolution (e.g., 12 bits) can record 18-hour real-time data within ~ 3.6-mm 2 chip area when the data storage is built with single-level cell (SLC) STT-RAMs. Daily energy consumption is 5.46 mJ. Utilizing the multilevel cell (MLC) STT-RAMs or the spintronic memristors as the storage elements can further reduce the chip area and decrease energy dissipation.

A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme

Among all the emerging memories, Spin-Transfer Torque Random Access Memory (STT-RAM) has demonstrated many promising features such as fast access speed, nonvolatility, excellent scalability, and compatibility to CMOS process. However, the large process variations of both magnetic tunneling junction (MTJ) and MOS transistors in the scaled technologies severely limit the yield of STT-RAM chips. In this work, we proposed a new sensing scheme, named as nondestructive self-reference sensing, or NSRS, for STT-RAM. By leveraging the different dependencies of the high and low resistance states of MTJs on the cell current amplitude, the proposed NSRS technique can work well at the scenario when bit-to-bit variation of MTJ resistances is large. Furthermore, we proposed three combined magnetic- and circuit-level techniques, including R-I curve skewing, yield-driven cell current selection, and ratio matching, to further improve the sense margin and robustness of NSRS sensing scheme. The measurement results of a 16 Kb STT-RAM test chip show that our proposed nondestructive self-reference sensing technique can reliably readout all the measured memory bits, of which 10% read failure rate was observed by using the conventional sensing technique. The three enhancement technologies ensure a 20 mV minimum sense margin and the whole sensing process can complete within 15 ns.

Spin-Transfer Torque Switching Above Ambient Temperature

We report the temperature dependences of tunneling magnetoresistance ratio, coercivity, thermal stability, and switching current distribution of magnetic tunnel junctions (MTJs) in the temperature range 25-80°C, the most probable working environment for spin-transfer torque random access memory (STT-RAM). Two distinct temperature dependence of the switching current density are apparent due to two switching mechanisms: a switching current density decrease with increasing temperature in the long-pulse ( >; 1 μs) regime, a result of thermally activated switching, but no decrease in the short-pulse (>;10 ns) regime, as a result of precessional switching. In the temperature range studied, the switching current density variation is less sensitive to environmental temperature than it is to switching time. Thus, switching time is the more important factor to consider in STT-RAM design.

Performance, Power, and Reliability Tradeoffs of STT-RAM Cell Subject to Architecture-Level Requirement

Large switching current and long switching time have significantly limited the adoption of spin-transfer torque random access memory (STT-RAM). Technology scaling, moreover, makes it very challenging to reduce the switching current while maintaining the reliability of magnetic tunneling junction (MTJ) to be similar to that of the earlier generations. In this work, we shall exploit a key insight that in the most on-chip caches where STT-RAM is most likely to be deployed, the lifespan of the data stored in the memory cells is much shorter than the data retention time requirement assumed in STT-RAM development, namely, 4~10 years. We also quantitatively investigated the possibility of trading off MTJ nonvolatility for improved switching performance, e.g., the switching time and/or current, under architectural level guidance. We further proposed and evaluated a hybrid memory design technique that partitions the on-chip STT-RAM cache into two parts with different nonvolatility performances so as to better fit the diverse retention time requirements of different data sets.

STT-RAM Cell Optimization Considering MTJ and CMOS Variations

Spin-transfer torque random access memory (STT-RAM) becomes a promising technology for future computing systems for its fast access time, high density, nonvolatility, and small write current. However, like all the other nanotechnologies, STT-RAM suffers from process variations and environment fluctuations, which significantly affect the performance and stability of magnetic tunneling junction (MTJ) devices. In this study, we combine magnetic and circuit simulations to quantitatively analyze the impacts of MTJ and CMOS variations on the STT-RAM designs. Both bit-to-bit and cycle-by-cycle variations are considered. A robust STT-RAM design flow is also proposed.

Nonpersistent Errors Optimization in Spin-MOS Logic and Storage Circuitry

By combining the flexibility of MOS logic and the nonvolatility of spintronic devices, Spin-MOS logic and storage circuitries offer a promising approach to implement a highly integrated, power-efficient, and nonvolatile computing and storage systems. Besides the persistent errors due to process variations, however, the functional correctness of Spin-MOS circuitries suffers from additional nonpersistent error that incurred by the randomness of spintronic device operations, i.e., thermal fluctuations. In this work, we quantitatively investigate the impacts of the thermal fluctuations on the operations of two typical Spin-MOS circuitries: one transistor and one magnetic tunnel junction (1T1J) spin-transfer torque random access memory (STT-RAM) cell and a nonvolatile flip-flop design. The possible design techniques to reduce thermal incurred nonpersistent error rate are also discussed. Our experimental results show that the optimization of nonpersistent and persistent errors are closely entangled with each other and should be conducted from both circuit design and magnetic device engineering perspectives simultaneously.

Simulation study of new 3-terminal devices for high speed STT-RAM

To improve the performance of spin transfer torque random access memory (STT-RAM), especially writing speed, we propose three modified 3-terminal STT-RAM cells. A magnetic dynamic process in the new structures was investigated through micro-magnetic simulation. The best switching speed of the new structures is 120% faster than that of the rectangular 3-terminal device. The optimized 3-terminal device offers high speed while maintaining the high reliability of the 3-terminal structure.

Challenges toward gigabit-scale spin-transfer torque random access memory and beyond for normally off, green information technology infrastructure (Invited)

If spin-transfer torque RAM (SPRAM) technology is used as a true nonvolatile RAM, it will be able to provide normally “off” and instant “on” functions. This would drastically reduce the power consumption of information technology (IT) equipment and its infrastructure while preserving high performance, thus leading to a green IT infrastructure. This paper describes the design issues and solutions for creating a Gb-scale SPRAM; scaling in memory cell current (∝F, F: feature size) and the tunneling magnetoresistive (TMR) device’s write current (∝F2), the maximum voltage applicable to a TMR device (TMR ratio and resistance area product are considered); and the thermal stability of the TMR device (depending on the operation mode and density). Moreover, the cell and array configurations and an indispensable disruptive reading operation are shown for 4F2DDRx compatible operations. SPRAM can cover a system composed of a DRAM region. Finally, the potential of a multibit memory structure that covers the area of a not-and flash memory is discussed.

Low writing energy and sub nanosecond spin torque transfer switching of in-plane magnetic tunnel junction for spin torque transfer random access memory

This work investigated in-plane MgO-based magnetic tunnel junctions (MTJs) for the application of spin torque transfer random access memory (STT-RAM). The MTJ in this work had an resistance area product (RA) = 4.3 Ω·μm2, tunneling magnetoresistance ratio ∼135%, thermal stability factor Δ(H)=68 (by field measurement), and Δ(I) = 50 (by current measurement). The optimal writing energy was found to be 0.286 pJ per bit at 1.54 ns for antiparallel (AP) state to parallel (P) state switching, and 0.706 pJ per bit at 0.68 ns for P state to AP state switching. Ultra fast spin torque transfer (STT) switching was also observed in this sample at 580 ps (AP to P) and 560 ps (P to AP). As a result, 0.6–1.3 GHz was determined to be the optimal writing rate from writing energy consumption of view. These results show that in-plane MgO MTJs are still a viable candidate as the fast memory cell for STT-RAM.

Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)

Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, spin-torque transfer random access memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (e.g., L2 or L3 cache) for microprocessors. Due to unique operational characteristics of its storage device magnetic tunneling junction (MTJ), STT RAM is inherently subject to a write latency versus read latency tradeoff that is determined by the memory cell size. This paper first quantitatively studies how different memory cell sizing may impact the overall computing system performance, and shows that different computing workloads may have conflicting expectations on memory cell sizing. Leveraging MTJ device switching characteristics, we further propose an STT RAM architecture design method that can make STT RAM cache with relatively small memory cell size perform well over a wide spectrum of computing benchmarks. This has been well demonstrated using CACTI-based memory modeling and computing system performance simulations using SimpleScalar. Moreover, we show that this design method can also reduce STT RAM cache energy consumption by up to 30% over a variety of benchmarks.