The Prospect of STT-RAM Scaling From Readability Perspective

Abstract

Due to its fast access time, high integration density, nonvolatility and good CMOS compatibility, Spin-transfer torque random access memory (STT-RAM) becomes one promising technology for the memory hierarchy of the next-generation computing systems. In recent years, tremendous efforts have been made to reduce the switching current of magnetic tunneling junction (MTJ) for write performance and energy improvement. However, the success of write current reduction makes the STT-RAM read stability issue more prominent during the scaling of STT-RAM: following the decrease in MTJ switching current, the read current must scale accordingly to keep the disturbance on the MTJ resistance state at a minimum level. If the MTJ resistance and/or TMR values do not increase proportionally, the effective sense margin of STT-RAM will degrade, leading to a higher sensing error rate. In this work, we quantitatively analyzed the impacts of existing MTJ scaling rule on the readability STT-RAM, including both read disturbance and sensing errors. We also presented the importance of selecting an optimal read current for maintaining the readability of STT-RAM under the current scaling trend.