Abstract
Spin-transfer torque random access memory (STT-RAM) has demonstrated great potentials as a universal memory for its fast access speed, zero standby power, excellent scalability and simplicity of cell structure. However, large process variations of both magnetic tunneling junction and CMOS process severely limit the yield of STT-RAM chips. In this paper, we propose a novel voltage-driven non-destructive self-reference sensing scheme (NDRS) to enhance the STT-RAM chip yield by significantly improving sense margin. Monte-Carlo simulations of a 16 Kb STT-RAM array shows that our proposed scheme can achieve the same yield as the previous NDRS scheme while improving the sense margin by 5 × with the similar access performance and power.
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