SPICE Simulation Research Articles

Estimation of bandwidth, voltage swing and DC coefficients for VLSI interconnects: current mode technique

ABSTRACT Necessity of bandwidth requires the effective use of it for high speed data transmission and faster read/write operation in memory cells. In this paper the transfer function expressions for RC interconnect line is presented for resistive load. The line delay, bandwidth and step response for current and voltage mode signalling is formulated. The current mode and voltage mode signalling provides the 3-dB bandwidth of 6.8 GHz and 3.1 GHz, respectively. An interconnect line modelled as either RLC or RC line depending upon input signal rise time, damping, and range of interconnect length with significant inductance effect is investigated for global interconnect lines. Low swing for column bit line in memory architectures is very important and estimated in terms of dc coefficients. For RC global interconnect of 10 mm, a swing of 0.382 V is obtained for current mode signalling, when a power supply of 1.8 V is applied to the network. DC coefficient and steady state value has been obtained which is significant for power computation on column bit line. It is also analytically validated by SPICE and MATLAB simulations.

P‐54: XAI Models for Efficient Analysis of Temperature and Power Consumption in High‐Brightness Panels and Modules

Predicting temperature and power consumption in panels and modules under high brightness has long been a daunting and time‐intensive task, often requiring over a week of simulation work. Addressing this challenge, our study introduces a novel machine learning framework, bifurcated into panel and module stages, to streamline the data acquisition process. A key innovation in our approach is the use of symbolic regression to overcome the limitations posed by the reliance on real‐world measurements for power consumption and heat generation. Employing SPICE simulations, we estimated the current density within the panel, with subsequent validation through Explainable AI (XAI) analysis. This revealed a significant correlation between current density and panel heat generation. Our research also revisits the traditionally neglected areas outside the panel's center, uncovering their impact on heat generation. The layered complexity in modules, previously a barrier to physical sample creation and measurement, was navigated using simulation. XAI insights demonstrated the crucial roles of graphite and metal layers in heat dissipation, and the drive IC as a primary heat source. This integrated approach of real and computational data in machine learning significantly reduced the analysis timeframe from a week to mere minutes, marking a breakthrough in predictive accuracy and efficiency for high‐brightness scenarios.

Sampling the user controls in neural modeling of audio devices

This work studies neural modeling of nonlinear parametric audio circuits, focusing on how the diversity of settings of the target device user controls seen during training affects network generalization. To study the problem, a large corpus of training datasets is synthetically generated using SPICE simulations of two distinct devices, an analog equalizer and an analog distortion pedal. A proven recurrent neural network architecture is trained using each dataset. The difference in the datasets is in the sampling resolution of the device user controls and in their overall size. Based on objective and subjective evaluation of the trained models, a sampling resolution of five for the device parameters is found to be sufficient to capture the behavior of the target systems for the types of devices considered during the study. This result is desirable, since a dense sampling grid can be impractical to realize in the general case when no automated way of setting the device parameters is available, while collecting large amounts of data using a sparse grid only incurs small additional costs. Thus, the result provides guidance for efficient collection of training data for neural modeling of other similar audio devices.

Development of a Flexible Sensor-Integrated Tissue Patch to Monitor Early Organ Rejection Processes Using Impedance Spectroscopy.

Heart failure represents a primary cause of hospitalization and mortality in both developed and developing countries, often necessitating heart transplantation as the only viable recovery path. Despite advances in transplantation medicine, organ rejection remains a significant post-operative challenge, traditionally monitored through invasive endomyocardial biopsies (EMB). This study introduces a rapid prototyping approach to organ rejection monitoring via a sensor-integrated flexible patch, employing electrical impedance spectroscopy (EIS) for the non-invasive, continuous assessment of resistive and capacitive changes indicative of tissue rejection processes. Utilizing titanium-dioxide-coated electrodes for contactless impedance sensing, this method aims to mitigate the limitations associated with EMB, including procedural risks and the psychological burden on patients. The biosensor's design features, including electrode passivation and three-dimensional microelectrode protrusions, facilitate effective monitoring of cardiac rejection by aligning with the heart's curvature and responding to muscle contractions. Evaluation of sensor performance utilized SPICE simulations, scanning electron microscopy, and cyclic voltammetry, alongside experimental validation using chicken heart tissue to simulate healthy and rejected states. The study highlights the potential of EIS in reducing the need for invasive biopsy procedures and offering a promising avenue for early detection and monitoring of organ rejection, with implications for patient care and healthcare resource utilization.

Temperature- and variability-aware compact modeling of ferroelectric FDSOI FET for memory and emerging applications

In this paper, we present a temperature and variability-aware Verilog-A-based compact model for simulating Ferroelectric FET. The model captures the rich physics of ferroelectric materials and the important electrical characteristics, such as the history effect, the impact of pulse width and amplitude on threshold voltage, and temperature-dependent degradation of polarization. The impact of variability is also explored regarding reliable operation of the FeFET. The developed model is robust and can accurately capture the experimentally observed trends, such as the change in polarization due to temperature, increased memory window on reading from the back-gate, etc. Further, we discuss two applications of our developed model viz. (a) multi-level-cell storage and (b) FeFET-based array for MAC operations. The designs are tested using the proposed model in commercial SPICE simulator at different temperatures including the effect of variation. Analysis presented in this article reveals that variability and temperature can be detrimental for operation of FeFET-based systems.

Comparative analysis of PMOS and NMOS based linear regulators with similar power profiles

In his article, a comparative analysis of PMOS and NMOS based linear voltage regulators is presented. An output power of 18 mW is considered in the both cases. In PMOS based regulator, the output voltage is 1.6 V and output current is 11.25 mA, whereas in NMOS, they are 1 V and 18 mA respectively. Firstly, a conventional linear regulator is designed with PMOS as pass element and its stability and various performance parameters are analyzed. SPICE simulation is carried out to measure parameters and they are tabulated for the comparison. Similarly, another linear regulator is designed where pass element is a NMOS transistor. After the analysis of stability and performance parameters, SPICE simulation is conducted. The performance parameters of both regulators are compared and it is found that NMOS regulator exhibits better performance but low dropout feature of PMOS regulator makes it suitable for low power applications

Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles

In his article, a comparative analysis of PMOS and NMOS based linear voltage regulators is presented. An output power of 18 mW is considered in the both cases. In PMOS based regulator, the output voltage is 1.6 V and output current is 11.25 mA, whereas in NMOS, they are 1 V and 18 mA respectively. Firstly, a conventional linear regulator is designed with PMOS as pass element and its stability and various performance parameters are analyzed. SPICE simulation is carried out to measure parameters and they are tabulated for the comparison. Similarly, another linear regulator is designed where pass element is a NMOS transistor. After the analysis of stability and performance parameters, SPICE simulation is conducted. The performance parameters of both regulators are compared and it is found that NMOS regulator exhibits better performance but low dropout feature of PMOS regulator makes it suitable for low power applications.

Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder

The Newcomb-Benford law, also known as Benford's law, is the law of anomalous numbers stating that in many real-life numerical datasets, including physical and statistical ones, numbers have a small initial digit. Numbers irregularity observed in nature leads to the question, is the arithmetical-logical unit, responsible for performing calculations in computers, optimal? Are there other architectures, not as regular as commonly used Parallel Prefix Adders, that can perform better, especially when operating on the datasets that are not purely random, but irregular? In this article, structures of a propagate-generate tree are compared including regular and irregular configurations—various structures are examined: regular, irregular, with gray cells only, with both gray and black, and with higher valency cells. Performance is evaluated in terms of energy consumption. The evaluation was performed using the extended power model of static CMOS gates. The model is based on changes of vectors, naturally taking into account spatio-temporal correlations. The energy parameters of the designed cells were calculated on the basis of electrical (Spice) simulation. Designs and simulations were done in the Cadence environment and calculations of the power dissipation were performed in MATLAB. The results clearly show that there are PPA structures that perform much better for a specific type of numerical data. Negligent design can lead to an increase greater than two times of power consumption. The novel architectures of PPA described in this work might find practical applications in specialized adders dealing with numerical datasets, such as, for example, sine functions commonly used in digital signal processing.

Rapid time-domain simulation of fractional capacitors with SPICE

Fractional capacitors, commonly called constant-phase elements or CPEs, are used in modeling and control applications, for example, for rechargeable batteries. Unfortunately, they are not natively supported in the well-used circuit simulator SPICE. This manuscript presents and demonstrates a modeling approach that allows users to incorporate these elements in circuits and model the response in the time domain. The novelty is that we implement for the first time a particular configuration of RC elements in parallel in a Foster-type network with SPICE in order to simulate a constant-phase element across a defined frequency range. We demonstrate that the circuit produces the required impedance spectrum in the frequency domain, and shows a power-law voltage response to a step change in current in the time domain, consistent with theory, and is able to reproduce the experimental voltage response to a complicated current profile in the time domain. The error depends on the chosen frequency limits and the number of RC branches, in addition to very small SPICE numerical errors. We are able to define an optimum circuit description that minimizes error while maintaining a short computation time. The scientific value is that the work permits rapid and accurate evaluation of the response of CPEs in the time domain, faster than other methods, using open source tools.

Nature inspired algorithm based design of near ideal fractional order low pass Chebyshev filters and their realization using OTAs and CCII

Fractional order filters offer greater freedom of design and a precise control over stopband attenuation in electronic circuits and systems. This paper presents the design of a fractional order low pass Chebyshev filter (FOLCF) that achieves near-ideal response characteristics. The methodology introduced utilizes metaheuristic optimization methods, including particle swarm optimization, firefly algorithm, and grey wolf optimization. These techniques are employed to precisely adjust the filter coefficients for the orders (1+α), (2+α), and (3+α). The adjustment is carried out by comparing the desired behaviour of the FOLCF with generalized fractional order low pass transfer functions. Throughout these instances, the parameter α is varied within the range of (0, 1). The designed filters are then tested and compared on the basis of various factors. Simulation results demonstrate that the designed filters closely follow the behaviour of an ideal Chebyshev filter with maximum passband and stopband magnitude errors being −31.93 dB and −52.74 dB respectively for (1+α) order filters. These values for (2+α) and (3+α) order FOLCF have been observed to be −30.04 dB and −55.91 dB; −17.72 dB and −49.52 dB respectively. Furthermore, it has been observed that the proposed work outperforms existing state-of-the-art approaches in various aspects, including magnitude error, stopband attenuation, and cut-off frequency. The stability of the designed filters has been verified through stability analysis. Additionally, practical feasibility of the proposed FOLCF is demonstrated through SPICE simulations for α = [0.2,0.5,0.8] using second generation current conveyor (CCII) and operational transconductance amplifier (OTA) based topologies while approximating the constant phase element using fifth order continued fraction expansion. The SPICE implementations closely follow the behaviour of ideal filter with −48.67 dB and −62.8 dB as mean square errors for CCII and OTA circuits respectively, showcasing the proposed filters' superiority and practical applicability in advanced electronic design.

SPICE simulation of the time-dependent clustering model for dielectric breakdown

In this letter, a method for dealing with the time-dependent dielectric breakdown (TDDB) of oxide layers in MOS and MIM structures in the framework of SPICE simulations is reported. In particular, we focus the attention on the clustering model (Burr’s XII distribution) for dielectric breakdown which can be considered an extension of the well known Weibull model. The oxide time-to-breakdown for both models is calculated using the inversion method for the cumulative distribution function. For the sake of completeness, the proposed approach includes uncorrelated variability both in the initial and final resistance states. For illustrative purposes, it is also shown how voltage acceleration, progressive breakdown or any other correlation factor can be introduced in the simulation parameters. As an application example, the proposed method is used to simulate the simplest case of a gate-to-drain dielectric breakdown of a NMOS-based inverter circuit.

CMOS Design of Chaotic Systems Using Biquadratic OTA-C Filters

This manuscript shows the CMOS design of Lorenz systems using operational transconductance amplifiers (OTAs). Two Lorenz systems are then synchronized in a master–slave topology and used to implement a CMOS secure communication system. The contribution is devoted to the correct design of first- and second-order OTA-C filters, using 180 nm CMOS technology, to guarantee chaotic behavior. First, Simulink is used to simulate a secure communication system using two Lorenz systems connected in a master–slave topology, which is tested using sinusoidal signals that are masked by chaotic signals. Second, the Lorenz systems are scaled to have amplitudes of the state variables below 1 Volt, to allow for CMOS design using OTA-C filters. The transconductances of the OTAs are tuned to accomplish a Laplace transfer function. In this manner, this work highlights the design of a second-order CMOS OTA-C filter, whose damping factor is tuned to generate appropriate chaotic behavior. Finally, chaotic masking is performed by designing a whole CMOS secure communication system by using OTA-C based Lorenz systems, and its SPICE simulation results show its appropriateness for hardware security applications.

Analysis of the behavior of TCAD and SPICE diode models in ESD protection circuits

To protect the interfaces of high-speed ICs from ESD, it is necessary to develop and optimize specialized protection circuit designs to minimize parasitic capacitance. The classic widely used designs based on ggMOS and SCR have too large parasitic capacitance, which degrades the parameters of the interface pins of the ICs. It is necessary to develop and optimize other ESD protection designs. One of the possible promising options is optimized diode protection. In this paper, an analysis of the effect of the design of a diode protection on its electrical characteristics is carried out. An analysis of the possibility of modeling protection using SPICE models was also performed and an assessment of the need to use TCAD simulation was carried out. Based on a comparison of the results of SPICE and TCAD simulations, it is shown that widely used SPICE diode models not optimal for designing and optimizing diode ESD protection. For this task, it is necessary to use TCAD simulation, taking into account the self-heating of the structure and the dynamics of the propagation of the thermal front. The results of this work are used for the development of ESD protection for interfaces of high–speed microcontrollers, DACs/ADCs, and transceivers.

The Silicon Charge Detector of the High Energy Cosmic Radiation Detection experiment

The High Energy Cosmic Radiation Detector (HERD) is an experiment designed for direct measurement of cosmic rays on the Chinese Space Station in 2027. Its goals include precise measurements of cosmic ray energy spectra, mass composition, electron/positron spectra, cosmic rays anisotropy, gamma ray astronomy and indirect searches for Dark Matter. HERD features a 55X0, homogeneous, 3D segmented imaging calorimeter and can detect particles from the top and four lateral sides, providing precise energy measurements and electron/proton separation for a wide field of view. A key detector in HERD is the Silicon Charge Detector (SCD). SCD measures the charge of particles before interaction with other materials, minimizing cosmic rays nuclei fragmentation and reducing systematics on nuclei flux measurement. Thorough studies, TCAD and/or SPICE simulations, and accelerator tests on prototypes have been conducted to evaluate the tracking and charge resolution capabilities of the SCD. Further testing with 300 μm detectors is planned in the coming months to fully characterize the SCD's performance. This paper presents the results of the simulation studies and of the measured performance with particles.

Automated design flow for synthesizable ADPLL: From specification to GDS

We propose an automated design flow for an all-digital phase-locked loop (ADPLL) that selects and implements a PLL layout that satisfies user given input specifications using place-and-route (PnR) tools within 1.2 h. The all-digital architecture enables the use of a theory-based frequency domain model for predicting the output specifications once the oscillator performance is characterized. The cell-based digitally controlled oscillator (DCO) is modeled by extracting the PDK and cell specific constants that characterize the effective current to capacitance ratio from only 3 sets of SPICE simulations. The constants are then used to predict the analog performance with an analytical model, which shows an error rate less than 1.5 % for estimating frequency range and power consumption. The generator guides the user to a feasible set of specifications using the analytical model by providing the achievable range of the failed specification. As design examples, 8 generated PLL designs and their post-parasitic performances are compared to input specifications, including one measurement result from a fabricated chip in 65 nm CMOS process.

WIRELESS TRANSMITTER FOR OPTICAL COMMUNICATION WITH FREQUENCY-MODULATED LASER CARRIER

Interest in the use of unguided optical systems is growing, due to the development of wireless mobile and indoor communication systems as well as the applications of lasers in space technology. The proposed laser transmitter, with frequency-modulated carrier, represents the optical transmitter of a wireless optical communication system, for transmitting audio signals on laser carriers, which can be used both inside buildings and outside, for distances estimated according to system parameters. In the paper are presented elements of design of the electrical diagram of principle, as well as analysis by SPICE simulation of the designed circuit. The results obtained by SPICE simulation synthesize the operation of the laser transmitter, allowing an optimization of the parameters of the component circuits.

Performance improvement for the CMOS rail-to-rail amplifier via APSO-based design and SNN’s training

This paper proposes an adaptive Particle Swarm Optimization(APSO) global search algorithm and Spiking Neural Network(SNN) surrogate model-based optimization design method for analog integrated circuits performance enhancement. The initial design parameters are calculated by numerical computation. The global design space is extended and explored using APSO in the main loop, with constraint testing ensuring the transistor works in the right conditions. A Spiking Neural Network (SNN) model aids in predicting circuit performance during local searches, in which training data for the local design space is generated through parallel SPICE simulations. The optimization framework is applied to rail-to-rail amplifiers of two topologies. The results show that the proposed method accelerates the optimization process, achieving up to a 35.4x speed enhancement compared to Particle Swarm Optimization(PSO) based on the SPICE simulation. Moreover, Compared with traditional approaches based on multiobjective optimization, the proposed method provides an advantage in performance improvement and is valid for different CMOS processes.

Insulator Metal Transition-Based Selector in Crossbar Memory Arrays

This article investigates resistive random access memory (ReRAM) crossbar memory arrays, which is a notable development in non-volatile memory technology. We highlight ReRAM’s competitive edge over NAND, NOR Flash, and phase-change memory (PCM), particularly in terms of endurance, speed, and energy efficiency. This paper focuses on the architecture of crossbar arrays, where memristive devices are positioned at intersecting metal wires. We emphasize the unique resistive switching mechanisms of memristors and the challenges of sneak path currents and delve into the roles and configurations of selectors, particularly focusing on the one-selector one-resistor (1S1R) architecture with an insulator–metal transition (IMT) based selector. We use SPICE simulations based on defined models to examine a 3 × 3 1S1R ReRAM array with vanadium dioxide selectors and titanium dioxide film memristors, assessing the impact of ambient temperature and critical IMT temperatures on array performance. We highlight the operational regions of low resistive state (LRS) and high resistive state (HRS), providing insights into the electrical behavior of these components under various conditions. Lastly, we demonstrate the impact of selector presence on sneak path currents. This research contributes to the overall understanding of ReRAM crossbar arrays integrated with IMT material-based selectors.

New Approaches for Realizing Transconductance-boosted VDTA Structures

This paper presents two new transconductance-boosted architectures of the voltage differencing transconductance amplifier (VDTA). The first architecture (VDTA-I) relies on the technique of transconductance enhancement using partial positive feedback which is realized through negative impedance implemented using a cross-coupled amplifier. The second architecture (VDTA-II) incorporates the concept of gate-to-source voltage enhancement using an inverting amplifier for transconductance boosting. Detailed mathematical formulations for computing transconductance gain and bandwidth are presented using high-frequency small-signal equivalent circuits of both propositions. The functionality of the proposals is validated through SPICE simulations using TSMC 0.18[Formula: see text][Formula: see text]m technology parameters. Both DC and AC analyses are carried out through simulations. An enhancement in transconductance gain of 140% is observed for VDTA-I whereas for VDTA-II it is found to be 53% in comparison to the conventional VDTA. The 3[Formula: see text]dB frequencies are recorded to be 160 and 630[Formula: see text]MHz, respectively. The PVT analyses are also carried out to test the efficacy of both propositions.

Realization of nth Order Wave Active Low-Pass Filter Using Differential Difference Current Conveyor

A wave active filter (WAF) based on a differential difference current conveyor (DDCC) is presented in this paper. An active filter formation depends entirely on wave quantity processing. The wave method is demonstrated for the basic wave active elements (WAEs) of active filters such as a series inductor and a shunt capacitor. The novelty of the proposed work is that the mathematical operations required to implement the wave active components, such as lossy integration-subtraction; subtraction; summation and inverter, are performed using the DDCC as an analog building block (ABB). Designing WAFs of lower to higher-order is extremely challenging, i.e., great motivation to propose a WFA using a CMOS-based DDCC for lower and higher-order low-pass Butterworth filter topologies. Additionally, the filter performances are verified through noise analysis, percentage total harmonic distortion (%THD) and Monte Carlo analysis. The proposed WFA is theoretically verified for [Formula: see text]th order low-pass Butterworth filter designs ([Formula: see text]) using DDCC-based WAEs and validated using SPICE simulations with [Formula: see text]m TSMC CMOS technology parameters for DDCC, operating on [Formula: see text][Formula: see text]V.