Performance improvement for the CMOS rail-to-rail amplifier via APSO-based design and SNN’s training

Abstract

This paper proposes an adaptive Particle Swarm Optimization(APSO) global search algorithm and Spiking Neural Network(SNN) surrogate model-based optimization design method for analog integrated circuits performance enhancement. The initial design parameters are calculated by numerical computation. The global design space is extended and explored using APSO in the main loop, with constraint testing ensuring the transistor works in the right conditions. A Spiking Neural Network (SNN) model aids in predicting circuit performance during local searches, in which training data for the local design space is generated through parallel SPICE simulations. The optimization framework is applied to rail-to-rail amplifiers of two topologies. The results show that the proposed method accelerates the optimization process, achieving up to a 35.4x speed enhancement compared to Particle Swarm Optimization(PSO) based on the SPICE simulation. Moreover, Compared with traditional approaches based on multiobjective optimization, the proposed method provides an advantage in performance improvement and is valid for different CMOS processes.