SPICE Simulation Research Articles

3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM

Monolithic 3D stacking of complementary FET (CFET) SRAM arrays increases integration density multi-fold while supporting the inherent SRAM advantages of low write power and near-infinite endurance. We propose stacking multiple 8-transistor CFET-SRAM layers on regular CMOS periphery to achieve an ultra-high-density array for computing-in-memory (CIM). CFET and regular CMOS (FinFET) devices are measured and calibrated with BSIM-CMG compact model. SPICE simulations are performed to evaluate the delay of CIM operation, power consumption, and analog computational error due to device non-linearity. The impact of device non-linearity on neural network inference accuracy is evaluated using the CIMulator simulation platform. Lower CFET current drive due to amorphous (deposited) silicon channel is shown to have negligible impact on CIM operational delay in many cases, as the maximum allowable current is limited by wiring resistance, not transistor drive strength while maintaining accurate weighted sum. Compared to regular 2D CMOS FinFET array. CFET SRAM cells show an improvement up to 57.19% in TOPS/W. Furthermore, the performance in TOPS/W mm 2 is improved up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19\times $ </tex-math></inline-formula> . A factor proportional to the number of stacked layers for monolithically stacked CFET SRAM cells, makes it highly promising for future edge intelligence.

Fully Binarized, Parallel, RRAM-Based Computing Primitive for In-Memory Similarity Search

In this brief, we propose a fully-binarized XOR-based IMSS (In-Memory Similarity Search) using RRAM (Resistive Random Access Memory) arrays. XOR (Exclusive OR) operation is realized using 2T-2R bitcells arranged along the column in an array. This enables simultaneous match operation across multiple stored data vectors by performing analog column-wise XOR operation and summation to compute HD (Hamming Distance). The proposed scheme is experimentally validated on fabricated RRAM arrays. Full-system validation is performed through SPICE simulations using open source Skywater 130 nm CMOS PDK demonstrating energy of 17 fJ per XOR operation using the proposed bitcell with a full-system power dissipation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$145~\mu \text{W}$ </tex-math></inline-formula> . Using projected estimations at advanced nodes (28 nm) energy savings of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx 1.5\times $ </tex-math></inline-formula> compared to the state-of-the-art can be observed for a fixed workload. Application-level validation is performed on HSI (Hyper-Spectral Image) pixel classification task using the Salinas dataset demonstrating an accuracy of 91%.

DESIGN SPACE EXPLORATION OF LOW POWER FULL ADDER ACROSS MULTIPLE LOGIC STYLES AND PROCESS

The signal processing in digital domain becoming ubiquitous, a full adder circuit module has gained prominence for its optimization in terms of its speed, power dissipation, noise margin and area. Further, with the advent of mobile applications on electronic devices, low power has emerged as an overriding design criterion. The proposed work aims to explore the design space of a low power full adder circuit and the implications of logic styles on power-delay trade-offs. Further, the issues impacting the selection of process for design for a given application are addressed. A 1-bit full adder circuit in static CMOS logic style and hybrid logic style is designed and optimized for low-power by carrying out exhaustive simulations using the LT spice simulator in 65 nm and 45 nm standard process to explore their power envelope, before low power process becomes necessary for design. Low power designs are demonstrated and the trade-offs with speed and area are explored.

Pressure sensor diaphragm modelling and deformation analysis

This paper develops Micro-electromechanical Systems-based pressure sensor diaphragms (MEMS). This paper aims to build, model, and test a MEMS-based diaphragm that uses numerous structures of the same area and material to sense differential pressure. Similar goals: Diaphragm deflection and sensitivity were studied using COMSOL multiphysics software. LTspice is a high-performance SPICE simulator with a graphical schematic capture interface. The diaphragm bends when pressure changes, affecting the substrate-diaphragm displacement in COMSOL and the voltage output in LTspice via changing the resistances of three sensors. Voltage output changes with diaphragm bending. Changing voltage and displacement indicate environmental pressure. This method improves instrument response. In this work, a circular diaphragm-based pressure sensor has higher displacement, sensitivity, and stress output responses than a square or rectangular one.

AN ACCURACY IMPROVEMENT TECHNIQUE FOR ON-CHIP CURRENT SOURCES

A new design technique for accuracy improvement of on-chip reference current sources is proposed. A mathematical model has been developed describing the operation of the proposed technique. Based on the obtained equations, the variation of the reference current caused by the changes in operating conditions and process inaccuracies of the technological should not exceed 1…2%. The proposed technique has been implemented in the design of on-chip reference current source circuit in 14 nm FinFet technology. Spice simulations performed for the developed circuit show less than ± 5% variation of the reference current in the -40...1250C temperature range considering the process variations in ±3 sigma range. The circuit keeps that accuracy for the supply voltage drop up to 0.66 V.

Enhanced Current-voltage Nonlinearity by Controlling Oxygen Concentration of TiO&lt;SUB&gt;x&lt;/SUB&gt; Buffer Layer for RRAM Passive Crossbar Array

As a next-generation memory, resistive random access memory (RRAM) is attracting attention for its fast speed and non-volatility. Nevertheless, an additional selecting element is required to solve the sneak path problem. However, nonlinear devices such as transistors and selectors not only degrade density of the RRAM array, but also increase difficulty of 3D integration. Therefore, in this study, we propose a method for improving the current-voltage (I-V) nonlinearity of an Pt/Al₂O₃/TiOSUBx/SUB/Ti/Pt RRAM. Oxygen concentration was controlled based on electrical flexibility of TiOSUBx/SUB encompassing metallic and semiconducting properties; and three devices with different TiOSUBx/SUB were fabricated. As the O/Ti atomic ratio increases from 1.31 to 1.74, the enhanced I-V nonlinearity was confirmed, which was also quantitatively verified through fitting with a hyperbolic sine function. Reflecting the measured nonlinearity, RRAM passive array was constructed and its read margin was investigated by SPICE simulation. As a result, it is demonstrated that the read margin was improved by increasing the nonlinearity. For TiOSUB1.74/SUB sample which exhibits the highest nonlinearity, a read margin of 22.97% was achieved in 2SUP7/SUP × 2SUP7/SUP array size. By increasing the nonlinearity of RRAM devices, it is expected that RRAM passive array can be utilized for future high-density storage class memory.

Multi-gate BCAT Structure and Select Word-line Driver in DRAM for Reduction of GIDL

In this article, we evaluate gate induced drain leakage that affects the refresh time of buried cell array transistor DRAM cells. We proposed a multi-gate BCAT structure to minimize gate induced drain leakage and modified the select word-line circuit to operate multi-gate buried cell array transistor by adding only one PMOS. In the multi-gate structure, by changing the gate voltage, the work function of the metal gate was adjusted to effectively mitigate the electric field formed in the drain region by approximately four orders. As an adopting multi-gate structure, band to band tunneling is suppressed and gate induced drain leakage current is reduced. We verified that the dual-gate structure had less leakage current than the poly-Si BCAT using the TCAD simulation. The reduction of leakage according to the number of gates is inferred by confirming the reduction in GIDL of the three-gate structure compared with the dual-gate structure. Furthermore, the SPICE simulation confirmed that the proposed select word-line circuit transmits different optimized voltages to multiple gates when it is off than while transferring the same voltage when on. This structure can also be extended for application to other DRAM structures, such as the vertical structure and 3D-stacked DRAMs.

BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation

One of the greatest challenges in integrated circuit design is the repeated executions of computationally expensive SPICE simulations, particularly when highly complex chip testing/verification is involved. Recently, pseudo-transient analysis (PTA) has shown to be one of the most promising continuation SPICE solvers. However, the PTA efficiency is highly influenced by the inserted pseudo-parameters. In this work, we proposed BoA-PTA, a Bayesian optimization accelerated PTA that can substantially accelerate simulations and improve convergence performance without introducing extra errors. Furthermore, our method does not require any pre-computation data or offline training. The acceleration framework can either speed up ongoing, repeated simulations (e.g., Monte-Carlo simulations) immediately or improve new simulations of completely different circuits. BoA-PTA is equipped with cutting-edge machine learning techniques, such as deep learning, Gaussian process, Bayesian optimization, non-stationary monotonic transformation, and variational inference via reparameterization. We assess BoA-PTA in 43 benchmark circuits and real industrial circuits against other SOTA methods and demonstrate an average of 1.5x (maximum 3.5x) for the benchmark circuits and up to 250x speedup for the industrial circuit designs over the original CEPTA without sacrificing any accuracy.

Impedance Coupled Voltage Boosting Circuit for Polyvinylidene Fluoride Based Energy Harvester.

Polyvinylidene fluoride (PVDF) is an emerging method for energy harvesting by fluid motion with superior flexibility. However, the PVDF energy harvester, which has a high internal impedance and generates a low voltage, has a large power transmission loss. To overcome this problem, we propose an impedance-coupled voltage-boosting circuit (IC-VBC) that reduces the impedance of the PVDF energy harvester and boosts the voltage. SPICE simulation results show that IC-VBC reduces the impedance of the PVDF energy harvester from 4.3 MΩ to 320 kΩ and increases the output voltage by 2.52 times. We successfully charged lithium-ion batteries using the PVDF energy harvester and IC-VBC with low-speed wind power generation.

SPICE-Compatible Equivalent Circuit Models for Accurate Time-Domain Simulations of Passive Photonic Integrated Circuits

Passive photonic integrated circuits (PICs) can be easily characterized in the frequency-domain, but their accurate time-domain performance evaluation is a hurdle for system-level designers, especially when dealing with resonant circuits having highly dispersive behavior, such as ring resonators. In this paper, a new equivalent circuit modeling and simulation approach is proposed, based on the Complex Vector Fitting algorithm, able to perform accurate and robust time-domain simulations of passive PICs directly in standard SPICE simulators. The proposed modeling technique starts from scattering parameters of passive PICs, and is able to capture linear and high order dispersion, backscattering, and wavelength dependent effects. Considering the different nature of optical and electronic signals, a novel concept of equivalent voltage and current for optical waveguides is proposed to simplify the optical to electronic ports conversion and to make it possible to connect and terminate the equivalent circuit models as needed in SPICE simulators, natively supporting bidirectional signal propagation in a waveguide. This work provides a precise and reliable solution to evaluate time-domain characteristics of passive PICs and to access any internal nodes within a circuit, such as the signals inside a ring resonator. Three examples of time-domain simulations of passive PICs in commercial SPICE simulators are presented to demonstrate the flexibility and advantages of the proposed technique.

AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device

Traditional CMOS-based von-Neumann computer architecture faces the issue of memory wall that the limitation of bus-bandwidth and the speed mismatch between processor and memory restrict the efficiency of data processing along with an irreducible energy consumption conducted by data movement, especially in some data-intensive applications. Recently, some novel in-memory computing (IMC) paradigms developed by utilizing the characteristics of different non-volatile memories provide promising ways to overcome the bottleneck of memory wall. Here, we propose a new IMC unit based on a memory array with the core element of magnetoelectric spin-orbit logic (MESO) device (AIMCU-MESO), in which the characteristics of the MESO device are exploited to achieve several in-memory logic operations with the functions of NAND, NOR, and XOR in the MESO-based memory array. With the aid of some transistor-based switches, these logic operations can be achieved between any two MESOs in the array. Furthermore, the computing process of a 1-bit full adder (FA) is achieved in AIMCU-MESO by the in-memory logic manner to demonstrate the ability of logic cascading. The result of SPICE simulation for achieving the 1-bit FA using MESO devices is demonstrated, and the performances are compared with other designs of spintronics-based devices. Compared to multilevel voltage-controlled spin-orbit torque–based magnetic memory, the proposed design demonstrates 71.4% and 49.2% reductions in terms of storage delay and logic delay, respectively.

Series RLC Resonant Circuit Used as Frequency Multiplier

Currently, the design of resonant power converters has only been developed while operating in the steady state, while the design operating in the transient stage has not been considered nor reported. This paper is interested in testing the performance of the resonant circuits operating in the transient stage and finding applications where benefits can be obtained from this form of operation. One application in which it is possible to obtain benefits from designing resonant circuits in the transient state is in the area of frequency multiplication. Usually, to achieve frequency multiplication, it is necessary to resort to complex methods and special devices that increase the complexity of the design and the total cost of the circuit. This paper evaluates the performance of a series RLC resonant circuit operating in the transient stage and with an underdamped response acting as a frequency multiplier, where the oscillation frequency of the current in the resonant tank is “n” number of times the switching frequency of the square voltage source at the input with a duty cycle of D = 50%. To validate the analysis, a circuit was designed to deliver an output power of 30 watts to a resistive load, where the switching frequency of the square voltage source at the input was 500 kHz. Since a multiplier value “n” equal to fifteen was chosen, the current in the resonant tank reached an oscillation frequency of 7.5 MHz. The design methodology was validated by simulations in SPICE, complying with the established design parameters.

B-open Defect: A Novel Defect Model in FinFET Technology

This article proposes an electrical analysis of a new defect mechanism, to be named as b-open defect, which may occur in nanometer technologies due to the use of the Self-Aligned Double Patterning (SADP) technique. In metal lines making use of the SADP technique, a single dust particle may cause the simultaneous occurrence of a bridge defect and an open defect. When the two defects impact the same gates, the electrical effects of the bridge and the open combine and exhibit a new specific electrical behavior; we call this new defect behavior a b-open. As a consequence, existing test generation methodologies may miss defect detection. The electrical behavior of the b-open defect is first analyzed graphically and then validated through extensive SPICE simulations. The test pattern conditions to detect the b-open defect are finally determined, and it is shown that the b-open defect requires specific test generation.

Cell-Based Synthesis of Multiple Analog Filter and Oscillator Topologies Employing Graph

A new synthesis methodology, which offers design harmony of multiple analog filter and oscillator topologies is presented. Vertices of a bipartite graph are defined with simple mathematical function, denoted as cell. Weight of the edges are denoted by relation operator. A general theory has been developed based on graph and a set of traversal rules conjugated with cell, to produce multiple number of second-order function (SOF) in terms of cells. Theoretical approach has been facilitated with operational transconductance amplifier (OTA)-based circuit realization of multiple filter and oscillator topologies, and abridged with algorithm, which may lead to virtual EDA tool and field programmable analog array (FPAA). The proposed synthesis approach is validated with SPICE simulation.

An optimal design of current conveyors using a hybrid-based metaheuristic algorithm

&lt;span lang="EN-US"&gt;This paper focuses on the optimal sizing of a positive second-generation current conveyor (CCII+), employing a hybrid algorithm named DE-ACO, which is derived from the combination of differential evolution (DE) and ant colony optimization (ACO) algorithms. The basic idea of this hybridization is to apply the DE algorithm for the ACO algorithm’s initialization stage. Benchmark test functions were used to evaluate the proposed algorithm’s performance regarding the quality of the optimal solution, robustness, and computation time. Furthermore, the DE-ACO has been applied to optimize the CCII+ performances. SPICE simulation is utilized to validate the achieved results, and a comparison with the standard DE and ACO algorithms is reported. The results highlight that DE-ACO outperforms both ACO and DE.&lt;/span&gt;

Low Energy, Non-Cortical, Graphene Nanoribbon-Based STDP Plastic Synapses

The realization of energy efficient, low area, and fast processing neuron and synapse circuits is of prime importance for unleashing neuromorphic computing full potential. In this paper, we introduce a graphene-based synapse, which can emulate Spike Timing Dependent Plasticity (STDP) and Short/Long Term Plasticity (STP/LTP) with variable signal amplitude and temporal dynamics. The synapse operation is validated by means of SPICE simulations, and its synaptic modulation ability is showcased through reinforcement learning within a Spiking Neural Network for robotic navigation with obstacles avoidance. Besides its functional versatility, the proposed graphene-based synapse can potentially occupy low active area ($ \approx 170{\kern 1pt} {\mathrm{n}}{{\mathrm{m}}^2}$≈170nm2) and operate at low voltage ($200{\kern 1pt} {\mathrm{mV}}$200 mV ). When compared with a biological brain synapse, its energy consumption per spike for a weight update operation ($0.5{\kern 1pt} {\mathrm{fJ}}$0.5 fJ ) is $20 \times $20× lower, while the processing speed is increased by six orders of magnitude. Such properties are essential desiderata for the realization of large scale neuromorphic systems, making the proposed graphene-based synapse an outstanding candidate for this purpose.

Efficient Learning Strategies for Machine Learning-Based Characterization of Aging-Aware Cell Libraries

Machine learning (ML)-driven standard cell library characterization enables rapid, on-the-fly generation of cell libraries, opening the door for extensive design-space exploration and other, previously infeasible approaches. However, the benefits of ML-based cell library characterization are strongly limited by its high demand in training data and the costly SPICE simulation required to generate the training samples. Therefore, efficient learning strategies are needed to minimize the required training data for ML models while still sustaining high prediction accuracy. In this work, we explore multiple active and passive learning strategies for ML-based cell library characterization with focus on aging-induced degradation. While random sampling and greedy sampling strategies operate with low computational overhead, active learning considers the performance of ML models to find the most valuable samples for training. We also introduce a hybrid approach of active learning and greedy sampling to optimize the trade-off between reduction in training samples and computational overhead. Our experiments demonstrate an achievable training data reduction of up to 77% compared to the state of the art, depending on the targeted accuracy of the ML models.

Rectifier Design for Highly Loaded Inductive Wireless Power Transfer Systems for Biomedical Applications

Power transfer efficiency (PTE) and harmonics are crucial performance parameters of the resonant rectifier design for low/medium coupling inductive wireless power transfer (WPT) systems used in wireless biomedical implants. The performance of a resonant rectifier degrades under higher loading and lower coupling conditions as the voltage available to the rectifier at the output of the receiver coil becomes low. As the diode turn-on impedance increases, diodes turn on incompletely, leading to non-linearities that reduce rectifier efficiency and output voltage. This work proposes a new rectifier design to increase efficiency and reduce harmonics by decreasing the diode turn-on impedance compared to traditional rectifier designs, such as resonant Half Wave Rectifier (HWR). The proposed rectifier design offers individual paths for RF and rectification signals, which reduces the non-linear loading on the receiver coil and improves diode turn-on performance. Measurement and SPICE simulation results show efficiency enhancement of 50% and reduction of harmonics by 6 dB for the proposed rectifier compared to HWR.

A compact circuit-level model for single-event burnout in SiC power MOSFET devices

This paper presents a compact circuit-level model for single-event burnout (SEB) in silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs). Key parameters of the equivalent circuit model of the MOSFET are analyzed and determined in detail, including nonlinear parasitic drain-source capacitance and nonlinear parasitic gate-drain capacitance. The effect of the parasitic bipolar junction transistor is considered and an iteratively optimized double-exponential current source is used to simulate the transient power current generated by incident heavy ions. The equivalent circuit model of the MOSFET is verified by comparing the SPICE simulation curves, TCAD simulation curves, and the curves in the SiC power double trench MOSFET’s datasheet (SCT3080KL). Then, the SEB is caused by heavy ions at various incident positions, linear energy transfer values, drain-source voltage (V ds), and gate-source voltage (V gs) using the TCAD and HSPICE simulations. Simulation results on the SPICE model coincide with the TCAD simulation results. Moreover, this compact model is used to predict the SEB threshold for devices with higher breakdown voltage ratings.

A Novel Memristive Neural Network Circuit and Its Application in Character Recognition.

The memristor-based neural network configuration is a promising approach to realizing artificial neural networks (ANNs) at the hardware level. The memristors can effectively simulate the strength of synaptic connections between neurons in neural networks due to their diverse significant characteristics such as nonvolatility, nanoscale dimensions, and variable conductance. This work presents a new synaptic circuit based on memristors and Complementary Metal Oxide Semiconductor(CMOS), which can realize the adjustment of positive, negative, and zero synaptic weights using only one control signal. The relationship between synaptic weights and the duration of control signals is also explained in detail. Accordingly, Widrow-Hoff algorithm-based memristive neural network (MNN) circuits are proposed to solve the recognition of three types of character pictures. The functionality of the proposed configurations is verified using SPICE simulation.