SPICE Simulation Research Articles

Measurement and modeling of effective cable parameters of unshielded conductors

PurposeCables are ubiquitous in electronic-based systems. Electromagnetic emission of cables and crosstalk between wires is an important issue in electromagnetic compatibility and is to be minimized in the design phase. To facilitate the design, models of different complexity and accuracy, for instance, circuit models or finite element (FE) simulations, are used. The purpose of this study is to compare transmission line parameters obtained by measurements and simulations.Design/methodology/approachTransmission line parameters were determined by means of measurements in the frequency and time domain and by FE simulations in the frequency domain and compared. Finally, a Spice simulation with lumped elements was performed.FindingsThe determination of the effective permittivity of insulated wires seems to be a key issue in comparing measurements and simulations.Originality/valueA space decomposition technique for a guided wave on an infinite configuration with constant cross-section has been introduced, where an analytic representation in the direction of propagation is used, and the transversal fields are approximated by FEs.

Thermal Modelling and Power Consumption Estimation of a Multi Floor Small Scale Building Using SPICE Simulator

This study is a part of a concrete sustainable development project introduced at university. A small scale genuine materials house (1/20 scale) with its green energy sources and electronic circuits management have been designed for educational and research purpose [1]. Thanks to a modular design and optional accessories, many thermal and electronic measurements and modelling are possible, like in a real house. A SPICE equivalent thermal behaviour modelling is proposed. Once validated, a case of study for a three floor small scale building is presented. Power consumption and insulation efficiency are analyzed. Main tendencies are checked after comparison with a real multi floor building. Results are finally discussed.

A programmable tunable active grounded and floating immittance circuit using CCTA and their applications

ABSTRACT This article presents a novel grounded and floating immittance circuit. It can simulate any one of the floating and grounded positive and negative inductor circuit, positive and negative capacitor circuit, and positive and negative resistor circuit. The novelty of the proposed circuit is its capability to provide positive and negative immittances without any change of passive component and matching condition. In addition, active realisations of positive and negative fractional order immittance circuits are presented. Thus, this paper presents 16 types of immittances which cover entire two-dimensional phase plane. Grounded immittance circuit uses one active block Current Conveyor Transconductance Amplifier (CCTA), one grounded MOS resistor and one grounded passive component while floating immittance circuit employs two CCTAs and three components. The immittance of the proposed circuits can be tuned by changing the bias current of CCTA and bias voltage of MOS resistor. The frequency responses of the proposed circuits are verified using SPICE simulation based on the 0.18 µm TSMC CMOS technology parameter. The performance of the proposed positive immittance circuits is demonstrated by active filter design using SPICE in conjunction with MATLAB. The performance of the proposed negative immittance circuit is demonstrated through inductance cancellation.

Recovering the carrier number conservation in SPICE simulation of PIN diodes and IGBT devices

In SPICE simulations of PIN diodes and IGBT devices using finite difference method, one discretizes an undepleted N− region into several equally spaced nodes with a time-dependent distance of Δx(t), and then transforms the ambipolar diffusion equation, a time–space partial differential equation, into a set of time-dependent ordinary differential equations. However, the time-dependent property of Δx(t) destroys the carrier number conservation. In this paper, we propose an approach to correct the effect of the Δx(t) by introducing an auxiliary system. It has the same total current and the total carrier number in the undepleted N− region as the real system, but has different electron and hole current components. The difference is caused by adding compensation current terms with the equal amplitude and opposite sign to the electron and hole current terms in the auxiliary system. These compensation current terms are proportional to the boundary speed of the undepleted N− region and do not change the total current. The auxiliary system can be easily solved using SPICE behavior models and its carrier density is a good approximation to the real one. Our simulations show that the compensation current correction is important for fast switching PIN diodes, but may not be very important in IGBT devices due to their large gate-related capacitance.

A spiking neuron implemented in VLSI

A VLSI implementation of a Silicon-Controlled Rectifier (SCR)-based Neuron that has the functionality of the leaky-integrate and fire model (LIF) of spiking neurons is introduced. The silicon-controlled rectifier is not straightforward to efficiently migrate to VLSI. Therefore, we propose a MOS transistor-based circuit that provides the same functionality as the SCR. The results of this work are based on Spice simulation using open libraries and on VLSI layout and post layout simulations for a 65 nm CMOS process.

Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks on Arbiter-PUFs and Their Derivatives

Unintentional uncontrollable variations in the manufacturing process of integrated circuits are used to realize silicon primitives known as physical unclonable functions (PUFs). These primitives are used to create unique signatures for security purposes. Investigating the vulnerabilities of PUFs is of utmost importance to uphold their usefulness in secure applications. One such investigation includes exploring the susceptibility of PUFs to modeling attacks that aim at extracting the PUFs’ behavior. To date, these attacks have mainly focused on a single PUF instance where the targeted PUF is attacked using the model built based on the very same PUF’s challenge–response pairs or power side channel. In this article, we move one step forward and introduce <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Cross-PUF</i> attacks where a model is created using the power consumption of one PUF instance to attack another PUF created from the same GDSII file. Through SPICE simulations, we show that these attacks are highly effective in modeling PUF behaviors even in the presence of noise and mismatches in temperature and aging of the PUF used for modeling versus the targeted PUF. To mitigate the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Cross-PUF</i> attacks, we then propose a lightweight countermeasure based on dual-rail and random initialization logic approaches called DRILL. We show that DRILL is highly effective in thwarting <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Cross-PUF</i> attacks.

Design Automation of a Dynamic Thorax-Like Mesh Phantom for Evaluating the Performance of Electrical Impedance Tomography System

Abstract&#x2014;Phantoms are used to evaluate, calibrate, and compare the performance of electrical impedance tomography (EIT) systems. This paper presents a dynamic thorax-like mesh phantom, which mimics the changes in electrical conductivity distribution within a human thorax at different time frames. Furthermore, element merging and contour smoothing, electrode placement techniques, and PCB design automation methods are proposed to simplify, optimize the mesh phantom, and reduce the hardware implementation cost. To verify the accuracy of the mesh phantom and its PCB, SPICE simulations and experimental testings are performed to obtain the conductance of the mesh phantom and reconstruct the images through the EIDORS software. These images achieve an image correlation coefficient (ICC) of 0.680 (model versus SPICE simulation) and 0.9098 (SPICE simulation versus measurement result), respectively. This demonstrates the validity of our proposed dynamic thorax-like mesh phantom.

A Technology Path for Scaling Embedded FeRAM to 28 nm and Beyond With 2T1C Structure

Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) ferroelectric random access memory (FeRAM) has been demonstrated in 130 nm node with 1T1C structure. To scale FeRAM to 28 nm or beyond, a high aspect ratio embedded dynamic random-access memory (eDRAM)-like 3-D cylinder capacitor is expected to ensure sufficient cell capacitance and sense margin. In this work, we investigate an alternative approach with 2T1C structure that takes advantage of a back-end-of-line (BEOL) oxide channel writing transistor, a small planar ferroelectric (FE) capacitor, and a silicon logic reading transistor. First, the proof-of-concept of 2T1C bit cell was experimentally demonstrated. Then, the scalability toward 28 nm or beyond was simulated with array-level parasitics. Thanks to the transconductance reading out mechanism, a 900 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> FE capacitor in 2T1C could significantly reduce energy consumption 6.4– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.6\times $ </tex-math></inline-formula> compared to the traditional 1T1C FeRAM with similar cell area at 28 nm. Moreover, the area ratio between the FE capacitor and the read transistor is investigated both experimentally and with SPICE simulation, where adjustment of the pulsing scheme is needed for the maximum sense margin to occur. Finally, the performance at 7 nm is estimated in terms of read/write energy and cell area.

Ring generator of neuron-like activity with tunable frequency

The aim of the work is to build a radiophysical generator of neuron-like activity with a frequency tunable in various ways, corresponding to modern ideas about the structure of the hippocampus and the generation of pathological epileptic rhythms in it. Methods. The elements of the generator are radio engineering implementations of the complete FitzHugh– Nagumo neuron and the electronic implementation of a chemical synapse in the form of a sigmoid function with a delayed argument. The simulation was carried out in the SPICE simulator. Results. Various ways of introducing delay into the coupling are considered: an ideal delay line, a phase filter with a rheostat, one tunable Bessel filter, and a sequence of non-tunable Bessel filters. For circuit implementation, the approach using a Bessel filter with a rheostat is recognized as optimal as a compromise between simplicity and minimization of signal distortion. The dependences of the oscillation frequency on the number of elements in the ring and the delay time are constructed. The bistability of generation regimes is studied for certain values of the parameters. The effect of inclusion of inhibitory elements (interneurons) in the circuit is considered. Conclusion. The constructed ring generator models the experimentally observed properties of the dynamics of epileptic discharge fundamental frequency in limbic epilepsy. It is able to reproduce the occurrence of oscillations as a result of external short-term driving, smooth and sharp frequency tuning, the coexistence of different modes with the same parameters.

Multiphase Digital Low-Dropout Regulators

In this work, multiphase digital low-dropout (MP-DLDO) regulators are designed with resonant rotary clocks (ReRoCs) in order to improve on the tradeoff of conventional DLDOs between current efficiency and transient response speed. The proposed DLDOs are multiphased, coined MP-DLDOs, designed with a clock-gated control technique to provide high current efficiencies along with transient response improvements at GHz frequency levels. The multiple phases within the MP-DLDO are served with ReRoCs that provide: 1) a robust high-speed low-power resonant clock distribution solution for the synchronous elements in the multiphase DLDO architecture and 2) improve the transient response characteristics (dynamic voltage scaling (DVS) speed and voltage ripple) while saving power in the controller circuitry. The proposed MP-DLDOs are distributed across the chip to achieve low voltage ripple. SPICE simulations are performed on post-layout, parasitic-extracted models to evaluate the MP-DLDO architecture on open-source digital cores, with performance metrics that include the voltage ripple reduction, transient response speed improvement, and power savings in the control logic. The proposed MP-DLDO architecture, evaluated on an RISC-V design, demonstrates a DVS speed of 6.5 V/μs and an output voltage ripple of 21.1 mV (38% reduction when compared to a conventional DLDO) with a sampling frequency of 2 GHz.

Stochastic Power Loss Analysis of Differential Power Processing

This article presents stochastic power loss analysis for differential power processing (DPP). A stochastic model is developed to analyze power loss scaling in a DPP system based on probability distributions of loads or sources. Scaling factors are introduced to describe how losses change with DPP system size and load or source power variance. Expected power losses of representative DPP topologies are analyzed and compared to losses of a conventional dc–dc converter with the same total switch die area and magnetic volume. The results quantify performance trends of DPP architectures. Models and scaling factors are verified with SPICE simulations and experimental results. The analytical framework, scaling factors, and quantitative models provide useful guidelines for designing large-scale DPP systems. This article is accompanied by a video file demonstrating the modeling procedures and the experimental setup.

An Efficient In-Memory Computing Architecture for Image Enhancement in AI Applications

Random Spray Retinex (RSR) is an effective image enhancement algorithm due to its effectiveness in improving image quality. However, the algorithm computing complexity and the required hardware resources and memory accesses hampered its deployment in many applications scenarios, for instance in IoT systems with limited hardware resources. With the rise of Artificial Intelligence (AI), the use of image enhancement has become essential to improve the performance for many emerging applications. In this paper, we propose the use of the RSR as a pre-processing filter before the task of semantic segmentation of low-quality urban road scenes. Using the publicly available Cityscapes dataset, we compare the performance of a pre-trained deep semantic segmentation network on dark noisy images and on RSR pre-processed images. Our findings confirm the effectiveness of RSR in improving segmentation accuracy. In addition, to address the computation complexity and suitability to edge devices, we propose a novel efficient implementation of the RSR using resistive random access memory (RRAM) technology. The architecture provides highly parallel analog in-memory computing (IMC) capabilities. A detailed, efficient and low latency implementation of the RSR using RRAM-CMOS technology is described. The design is verified using SPICE simulations with measured data from fabricated RRAM and 65nm CMOS technologies. The approach provided here represents an important step towards low-complexity and real-time hardware-friendly architecture and design for Retinex algorithms for edge devices.

Analytical Calculation of the RMS Value and the Spectrum of the DC-Link Current of a Dual-Inverter

This article is focused on the analytic definition of the dc-link current of a dual-inverter. Therefore, a two-level dual-inverter for driving two independent three-phase electrical motors is considered. Space-vector modulation is taken into account as the modulation method of the inverter. Based on that, an analytic description is derived for the frequency spectrum as well as for the rms value of the dc-link current of a dual-inverter. Contrary to the current definitions known from previous publications, the expressions presented below are defined in solved form. Therefore, the use of integral or differential equation expressions is not necessary. In this way, a basis is created for calculating the dc-link current without computationally intensive numerical integration processes or SPICE simulations. Furthermore, this article includes the metrological verification of the novel expressions. The results discussed in this publication provide the basis for stabilizing the HV-dc system and for minimizing the dc-link capacitor load. Thus, they enable the dc-link capacitor of a dual-inverter to be downsized. Based on the presented definition of the dc-link current in solved form, the possibility of real-time optimization is created. Furthermore, the results outlined in this article form the foundation to derive the control optimization for a multiphase inverter.

NOISE ANALYSIS AND OPTIMIZATION OF GENERAL OTA-C FILTERS

In the paper, a general approach to noise analysis in continuous-time OTA-C filters is presented. Recently an increasing interest in the design of continuous-time filters based on the transconductance capacitor (OTA-C) technique has been observed. The operational transconductance amplifiers (OTAs) offer a higher bandwidth than their voltage-mode counterparts, can be easily tuned electronically, and have a better suitability for operating in reduced supply environment. Due to this, high frequency integrated filters are mostly realized as the OTA-C ones. Based on a matrix description of a general OTC filter topology, a universal formulas for evaluating the noise in any OTC filter are derived. The presented formulas can be easily implemented and used in computer-aided analysis/optimization software. The accuracy of the proposed method is confirmed by comparison with SPICE simulation. The example of application for finding the minimum-noise 5th order multiple-loop feedback filters implementing Butterworth and Bessel transfer functions is given.

Compact Modeling and SPICE Simulation of GCMO-Based Resistive Switching Devices

This letter reports a compact behavioral model for the hysteretic conduction characteristics of Al&#x002F;Gd_0.1Ca_0.9MnO₃(GCMO)&#x002F;Au resistive switching devices suitable for SPICE simulations. The devices are nonvolatile, forming-less, compliance-free, and self-rectifying multistate memristive structures which makes them of maximum interest for neuromorphic computing and memory applications. The proposed model relies on two coupled equations, one for the electron transport and a second one for the vacancy displacement. First, the fixed and variable current components that contribute to the total electronic flow are identified and modelled. They are tunneling and diode-like conduction with series resistance through the thin sub-oxide layer formed at the GCMO&#x002F;Al interface in combination with filamentary conduction. Second, the memory equation accounts for the reversible movement of vacancies that causes the generation and self-healing of these micro-filaments. Importantly, the proposed model considers a novel approach for solving the internal state of the device based on the so-called generalized quasi-static hysteron whose application can be extended to other structures and dynamics in addition to the ones discussed here.

Crosstalk Analysis of On-chip VLSI Interconnects

In this paper dynamic crosstalk is analyzed for coupled on-chip VLSI interconnects in different conditions. The proposed work has taken the MOS transistor analytical expressions. In this work, calculated the transition delays and different timings of the interconnect aggressor and interconnect victim drivers for in-phase switching and out-of-phase switching. All the calculated results are compared with simulations in SPICE. The average error in the transmission delay using SPICE is 2.02 and 3.274% for the interconnect aggressor and interconnect victim buffers for in phase switching, respectively. The average errors in the same are 2.3 and 1.87% for out phase switching event.

Hybrid Data-Driven Modeling Methodology for Fast and Accurate Transient Simulation of SiC MOSFETs

To enable fast and accurate models of SiC MOSFETs for transient simulation, a hybrid data-driven modeling methodology of SiC MOSFETs is proposed. Unlike conventional modeling methods that are based on complex nonlinear equations, data-driven artificial neural networks (ANNs) are used in this article. For model accuracy, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$I$</tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V$</tex-math></inline-formula> characteristics are measured in the whole operation region to train the ANN. The ANN model is then combined with behavior-based equations to model the cutoff region and to avoid overfitting the ANN. In addition, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$C$</tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$V$</tex-math></inline-formula> characteristics are modeled by ANNs with a logarithmic scale for accuracy. The proposed model is implemented and simulated in SPICE simulator SIMetrix. The simulation results are compared with experimental results from a double pulse tester to validate the proposed modeling methodology. The model is also compared with the Angelov model created by the Keysight MOSFET modeling software. The comparison results show that the proposed model is more accurate than the Angelov model. Besides, when compared to the Angelov model, the proposed model requires 30% less computation time when simulating a double pulse tester. In addition, the proposed modeling method also has better adaptability to model different types of SiC MOSFETs.

A Software-Circuit-Device Co-Optimization Framework for Neuromorphic Inference Circuits

Neuromorphic circuits, which usually use analog computation for vector-matrix multiplication (VMM) in neural networks (NN), are promising machine learning accelerators with much lower latency and power consumption than digital ones. Analog computation is expected to have a more efficient design space than digital computation since the signals are not digitized. Therefore, it is very suitable for Internet-of-Thing (IoT) applications that require ultra-low power consumption at a low cost. For IoT applications, sometimes it is also desirable to eliminate the digital circuits (such as adders, registers, shifters, multiplexers, and Analog-to-Digital Converters) between the VMM arrays to further reduce the power consumption. However, the optimization of a purely analog circuit is more difficult and requires full SPICE circuit simulations. In this paper, we present a software-circuit-device co-optimization framework using a python wrapper for automatic full circuit SPICE simulation and analysis for neuromorphic circuits. This framework allows users to experiment with how the NN design (software) affects the performance of the hardware neuromorphic circuits. It takes Verilog-A or SPICE models from calibrations or PDK in various technologies and emerging memories (such as ReRAM) without further calibration (unlike using behavior models). We show that the simulation time is reasonable even with hundreds of thousands of synapses under limited computation resources. Using ReRAM and a 45nm generic technology as an example, the effects of feedback network and OpAmp design, software ML architecture, and input data accuracy on the inference accuracy are studied.

A capacitor-free fast-response low-dropout voltage regulator

An off-chip capacitor-free low-dropout (LDO) regulator using an improved frequency compensation scheme is proposed. The proposed LDO regulator employs a class-AB error amplifier and a load-current tracker. Outstanding line regulation, load regulation and transient response are achieved. SPICE simulation based on SMIC 0.35 µm CMOS technology shows that the proposed LDO regulator has a low frequency gain over 100 dB and a unity-gain bandwidth in the MHz range. In terms of transient response, the 1% settling time is shorter than 0.2 µs.

Design of a STT-MTJ Based Random-Access Memory With In-situ Processing for Data-Intensive Applications

During the last few years, deep learning techniques are frequently applied in large-scale image processing, detection in a variety of computer vision, cognitive tasks, and information analysis applications. The execution of deep learning algorithms like CNN and FCNN requires high dimensional matrix multiplication, which contributes to significant computational power. The frequent data movement between memory and core is one of the main reasons for considerable power consumption and latency, hence becoming a major performance bottleneck for conventional computing systems. To address this challenge, we propose an in-memory computing array that can perform computation directly within the memory, hence, reducing the overhead associated with data movement. The proposed Random-Access Memory with in-situ Processing (RAMP) array reconfigures the emerging magnetic random-access memory to realize logic and arithmetic functions inside the memory. Furthermore, the array supports independent operations over multiple rows and columns, which helps in accelerating the execution of matrix operations. To validate the functionality and evaluate the performance of the proposed array, we perform extensive spice simulations. At 45nm, the proposed array takes 5.39 ns, 0.68 ns, 0.68 ns, 0.7 ns and consumes 2.2 pJ&#x002F;bit, 0.21 pJ&#x002F;bit, 0.23 pJ&#x002F;bit, 0.7 pJ&#x002F;bit while performing a memory write, memory read, logic, and arithmetic operations respectively.