SPICE Simulation Research Articles

Design and Analysis of Approximate 4-2 Compressor for Efficient Multiplication

Approximation computing concepts have been introduced and studied to provide sufficient accuracy with low power. Many approximate 4-2 compressor designs and methods are proposed to build approximate multipliers. However, most of the designs used for conventional approximate multipliers have been proposed to achieve low power by compromising accuracy or to maintain accuracy with low performance. In this study, a new 4-2 compressor is proposed to improve the error rate, delay, and power consumption. The proposed compressor was used to build an approximate multiplier. Transistor-level SPICE simulations with a high-performance 32-nm predictive technology model (PTM) were conducted to verify the efficiency of the proposed design. The results show that the proposed 4-2 compressor design can achieve up to 4.2% and 22.5% improvement in power consumption and delay, respectively. The proposed multiplier design can achieve up to 4.2% and 15.5% improvement in power consumption and error metrics, respectively. Compared to other designs, the proposed multiplier has lower error in small operand operations.

Design of FinFET based low power, high speed hybrid decoder for SRAM

This paper proposes a novel FinFET based hybrid logic design for line decoders, which comprises of transmission gate logic (TGL), modified gate diffusion input (MGDI) logic and conventional NAND based FinFET logic. The 2–4 FinFET based decoder is designed using two topologies: (i) a 14- transistor topology for low power dissipation and lesser area and (ii) a 15-transitor topology for high-speed performance. Using the two topologies mentioned above, both inverting and non-inverting decoders of size 2–4 and 4–16 are designed. SPICE simulations of the proposed decoders are done at 45 nm CMOS and FinFET technologies and compared with different logic styles such as conventional logic, MGDI, mixed logic, and mixed MGDI logic at different frequencies with varying supply voltages and the proposed design outperforms other logic styles compared. The proposed FinFET hybrid decoder exhibits 6% and 77% lower power; 11.6% and 61.26% lower delay; 17% and 91.10% lower PDP respectively compared to the FinFET mixed decoder and CMOS hybrid decoder.

Pre-Emphasis Pulse Design for Reducing Bit-Line Access Time in NAND Flash Memory

This paper describes pre-emphasis (PE) pulses to reduce bit-line (BL) access time in NAND flash memory. Optimum PE pulse widths and resultant minimum BL delay times are investigated, where the BL delay is determined by the sense current at the input terminal of a sensing circuit in contrast with the word-line (WL) delay that is determined by the WL voltage at the gate of a selected memory cell. Two BL models are used, namely, a single-line model (SLM) for the shielded BL read operation and a three-line model (TLM) for the all-BL read operation. Under the condition that the sense current delay is defined by the time when the sense current becomes stable between 110% and 90% of the cell current and the BL voltage delay is defined by the time when the BL voltage at the selected cell reaches a window between 110% and 90%, SPICE simulation results show that the sensed current delay and the BL voltage delay are reduced by 43% and 36% in the case of SLM and by 16% and 28% in the case of TLM, respectively. Thus, the key results are the following: (1) PE pulses are effective to reduce the sense current delay time for BL access, as well as the BL voltage delay time for both SLM and TLM; (2) the sensitivity of the PE pulse on the delay time is much larger for the sensed current delay than the BL voltage delay due to the absence of filtering with the RC delay element in BL delay; and (3) address-dependent PE pulse control can reduce the sense current delay significantly, especially for access to cells closely located to the sensing circuit.

Systematic realization of non-linear arithmetic functions using hexagonal Field Programmable Analog Array

In spite of being the most popular reconfigurable platform for analog and mixed-mode design implementation, Field-Programmable Analog Array (FPAA) structures are limited to analog filters, amplifiers and communication circuits. Hexagonal FPAA is an established alternative to classical square-lattice FPAA but suitable architectures have not been cultivated much. In this paper, a hexagonal FPAA, implementing different nonlinear functions, eliminating global interconnections, and employing a graph-based mapping algorithm, has been proposed. For communication among the fundamental blocks and reconfiguration, it uses a local interconnection network consisting of central and corner switch blocks. The proposed mapping algorithm uses directed graph representations of fundamental blocks and desired circuits to map the nonlinear functions in the presented FPAA. Weights have been assigned to the graphs and manipulated for efficient placement and routing. All the theoretical predictions have been validated through SPICE simulation using 65 nm CMOS technology. The proposed architecture and mapping algorithm can be extended for large-scale FPAA enriched with automatic placement and routing tools.

Three new CFOA-based SIMO-type universal active filter configurations with unrivalled features

In this paper, three new single-input-multiple-output (SIMO)-type second order universal active filter (UAF) configurations, each employing only four current feedback operational amplifiers (CFOA), are proposed which offer the following attractive features simultaneously: (i) realisability of all the five generic filter functions viz. low pass filter, high pass filter, band pass filter, band reject filter and all-pass filter from the same configuration (ii) tunability of the pole frequency (ω0), quality factor (Q0)/bandwidth (BW) in all the five responses (iii) tunability of gain (H0) in most of the responses (iv) ideally infinite input impedance and ideally zero output impedance in all the cases and (v) employment of two grounded-capacitors, as preferred for IC implementation. To the best knowledge of the authors, these features of the presented new circuits are unrivalled by the other SIMO-type CFOA-based UAF biquads published earlier as none of them provide all the above mentioned advantages simultaneously while using only four CFOAs and two grounded capacitors. The workability of the proposed UAF structures has been demonstrated by SPICE simulation results as well as the experimental results using the commercially available AD844-type IC CFOAs.

Design of Switched-Capacitor DC-DC Voltage-Down Converters Driven by Highly Resistive Energy Transducer

Electrostatic vibration energy transducers have a relatively high output impedance (RET) and open-circuit voltage (VIN), so that voltage-down conversion is required for sensor/RF ICs. Switched-capacitor converters are the best candidate to create small-form-factor technology and are a low-cost solution because of their capability to fully integrate into sensor/RF ICs. To design switched-capacitor voltage-down converters (SC-VDCs) with a minimum circuit area for electrostatic vibration energy transducers, two steps are required. The first step requires an optimum design of DC-DC SC-VDCs driven by high RET with a minimum circuit area, and the second step requires an optimum design of AC-DC SC-VDCs based on the first step, to minimize the converter circuit area. This paper discusses circuit analysis and design optimization aimed at the first step. Switching frequency, the number of stages and the capacitance per stage were determined as a function of RET, VIN and the output voltage (Vo) and current (Io) to the load, to achieve a minimum circuit area. The relationship between Io and the power conversion efficiency was studied as well. The performance was validated by SPICE simulation in 250 nm BCD technology. An optimum design flow was proposed to design DC-DC SC-VDCs driven by high RET with a minimum circuit area under conditions where RET, VIN, Vo and Io were given. The second design step remains as future work.

A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process

To maintain performance increase and reliability, power supply and threshold voltages will have to continually scale, in CMOS technology. With threshold voltage scaling and thinner gate-oxide thickness, sub-threshold and gate tunneling leakage powers are expected to become a significant portion of the total power in CMOS VLSI systems. A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this paper. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB and their performance is evaluated using SPICE simulations in 22 nm CMOS BSIM4 process. Evaluation outcomes with VDD = 0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates. The mentioned features of the proposed static-CMOS circuits are achieved while sustaining the full-swing behavior. To ensure the stability and robustness of the circuits in the presence of the process, voltage, and temperature (PVT) variations, Monte Carlo analysis is also performed.

Modeling and SPICE Simulation of the CdS/CdTe Neutron Detectors Integrated With Si-Poly TFTs Amplifiers

In this work, it is presented a unified model to integrate a radiation detector on a single chip using TFTs-based amplifiers, to fabricate a low-cost thermal neutron detector system. The model is based on the current-voltage experimental measurements of the CdS/CdTe detector and CMOS Si-Poly TFTs technology. Parameters obtained by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I-V$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$ </tex-math></inline-formula> - <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> analysis were introduced into Smart SPICE to design the amplifiers. The output voltage was simulated for a neutron capture event. Three amplification topologies were studied, obtaining an output voltage in the range of 180 to 260 mV with a generated photocurrent pulse around 3.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> , which is high enough to be interfaced with a microcontroller. The neutron detector is integrated into TFT amplifiers with a gain of around 50 dB and bandwidth of 4.7 MHz at −3 dB.

Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon

Near-threshold computing is essential for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, in this article, we propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime. Precisely, 1) we formulate the problem of finding an efficient configuration of monitoring circuits into an instance of optimal experiment design problem and 2) propose a new timing prediction flow, consisting of statistical estimation of FEOL and BEOL process variations and a neural network-based timing inference model. For accurate control of timing margin and overcoming simulation-silicon discrepancies, 3) we introduce uncertainty learning in the prediction model construction and calibrate it through transfer learning. Furthermore, 4) we avoid time-consuming SPICE simulations in our methodology by employing efficient but accurate surrogate models. Through simulations using a 28-nm industry PDK and DK characterized at 0.6-V operation, it is shown that our methodology is highly effective, reducing the average prediction pessimism of maximum delay by 77.9% over conventional signoff results while respecting target prediction yield. Besides, for test chips fabricated using a 10-nm process, we demonstrated that our holistic approach from design to postsilicon phase in conjunction with adaptive voltage scaling reduces dynamic power consumption by 28.2%–28.8% on average, in comparison with typical supply voltage operation.

On-chip learning of a domain-wall-synapse-crossbar-array-based convolutional neural network

Abstract Domain-wall-synapse-based crossbar arrays have been shown to be very efficient, in terms of speed and energy consumption, while implementing fully connected neural network algorithms for simple data-classification tasks, both in inference and on-chip-learning modes. But for more complex and realistic data-classification tasks, convolutional neural networks (CNN) need to be trained through such crossbar arrays. In this paper, we carry out device–circuit–system co-design and co-simulation of on-chip learning of a CNN using a domain-wall-synapse-based crossbar array. For this purpose, we use a combination of micromagnetic-physics-based synapse-device modeling, SPICE simulation of a crossbar-array circuit using such synapse devices, and system-level-coding using a high-level language. In our design, each synaptic weight of the convolutional kernel is considered to be of 15 bits; one domain-wall-synapse crossbar array is dedicated to the five least significant bits (LSBs), and two crossbar arrays are dedicated to the other bits. The crossbar arrays accelerate the matrix vector multiplication operation involved in the forward computation of the CNN. The synaptic weights of the LSB crossbar are updated after forward computation on every training sample, while the weights of the other crossbars are updated after forward computation on ten samples, to achieve on-chip learning. We report high classification-accuracy numbers for different machine-learning data sets using our method. We also carry out a study of how the classification accuracy of our designed CNN is affected by device-to-device variations, cycle-to-cycle variations, bit precision of the synaptic weights, and the frequency of weight updates.

SPICE model for complementary resistive switching devices based on anti-serially connected quasi-static memdiodes

This paper reports the use of the Quasi-static Memdiode Model (QMM) for simulating Complementary Resistive Switching (CRS) devices. CRS arises from the anti-serial connection of two memristors and it is used for generating low and high-resistance regions in the I-V characteristic with the aim of mitigating the sneak-path conduction problem in crossbar arrays. Here, the use of the QMM for CRS in the form of a six terminal subcircuit is explored. While two terminals of the subcircuit correspond to the conventional input and output pins of the CRS structure, the rest provide information about the voltage at the central node, the low-voltage conductance of each device, and the low-voltage conductance of the whole structure. Special attention is paid to the simulation of the so-called table with legs hysteresis loop (resistance at fixed bias vs. write voltage), which is often invoked in connection with devices that exhibit switching activity at the two interfaces of a single dielectric layer. Because of the internal potential drop distribution, the switching process takes place alternately at one side of the structure or the other giving rise to a pseudo-CRS behavior. The flexibility of the proposed approach is demonstrated through a series of fitting exercises that involve experimental data reported in the literature. The model script for the SPICE simulator is also provided.

Capacitance Characteristics Behavior of 0.5 Order FC Using CFOA Based FC Multiplier

This paper presents a method for capacitance scaling of Fractional Capacitor (FC) which is implemented using Current Feedback Operational Amplifiers (CFOA) based Capacitance Multipliers (C Multipliers). The circuit facilitates the change in FC value without changing component values in R-C network used for FC modelling or fabricating a new FC. The performance of the proposed circuit is examined for non ideal effects of CFOA. Effective impedance of scaled FC is examined through MATLAB simulations. The functionality of the realized scalers is verified using SPICE simulations where the FC is modelled using domino RC ladder network. Simulation results for impedance magnitude and phase responses are presented for various scaling factors and are compared with theoretical counterparts. The circuit application of proposed FC scaler is demonstrated through implementation of fractional order lossy and lossless integrators; and may be extended to fractional order filters, oscillators, controllers etc.

Comparative evaluation of SiC/GaN “MOSFET” transistors under different switching conditions

The aim of this paper is to conduct a mutual comparison of switching energy losses in cascade gallium nitride (GaN) and silicon "super junction" MOSFET” transistor, in both cases designed for a maximum operating voltage of (650 V). For the analysis of switching characteristics of transistors used double pulse test method by using detailed SPICE simulation model. Data on transient on and off processes were generated using the “LTspice” simulation package in a wide range of drain currents with two different gate resistance values of the tested transistors. The total energy losses in the GaN have been simulated during one transistor at (on and off cycle). The obtained results indicate that the superior switching characteristics of GaN devices for a drain current of (30 A) is five to eight times less than the switching characteristics of silicon “MOSFET” transistor when compared to silicon components, especially during operation of transistors with high drain currents.

ESD HBM Discharge Model in RF GaN-on-Si (MIS)HEMTs

Gallium nitride (GaN) technologies have become an essential role in commercial advanced RF systems, which accompany emerging RF electrostatic discharge (ESD) reliability challenges. As opposed to ESD clamp transistors in <i>LV</i> CMOS technologies, a mis-correlation between standard-defined human body model (HBM) ESD robustness and commonly used TLP failure current was observed in GaN (MIS) high electron mobility transistors (HEMTs). Using transient HBM <inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics, a novel discharge model is proposed to explain the transient discharge mechanism. The TCAD and SPICE simulations confirmed that the observed mis-correlation between TLP and HBM is attributed to 2-dimensional electron gas (2DEG) resistance modulation in response to HBM ESD transient voltage waveforms. The HBM waveforms under full transient duration in terms of rising and falling edges are further discussed. Eventually, the failure mechanisms in the TLP IVs and the HBM transient IVs can be well correlated in GaN (MIS)HEMTs.

Low Voltage High Performance Floating Gate and Quasi Floating Gate CDTA

A low voltage and low power current differencing transconductance amplifier (CDTA) based on Floating gate MOSFET (FGMOS) and Quasi-floating gate MOSFET (QFGMOS) is presented. The use of QFGMOS eliminates confined in the floating gate, degraded gain-bandwidth product, silicon area etc. The proposed circuits have been simulated using spice simulation software 180nm technology of analog devices LtSpice XVII and supply voltage used for this is ±1V.

An Evaluation of Power Side-Channel Resistance for RNS Secure Logic

In this paper, residue number system (RNS) based logic is proposed as a protection against power side-channel attacks. Every input to RNS logic is encrypted as a share of the original input in the residue domain through modulus values. Most existing countermeasures enhance side-channel privacy by making the power trace statistically indistinguishable. The proposed RNS logic provides cryptographic privacy that also offers side-channel resistance. It also offers side-channel privacy by mapping different input bit values into similar bit encodings for the shares. This property is also captured as a symmetry measure in the paper. This side-channel resistance of the RNS secure logic is evaluated analytically and empirically. An analytical metric is developed to capture the conditional probability of the input bit state given the residue state visible to the adversary, but derived from hidden cryptographic secrets. The transition probability, normalized variance, and Kullback–Leibler (KL) divergence serve as side-channel metrics. The results show that our RNS secure logic provides better resistance against high-order side-channel attacks both in terms of power distribution uniformity and success rates of machine learning (ML)-based power side-channel attacks. We performed SPICE simulations on Montgomery modular multiplication and Arithmetic-style modular multiplication using the FreePDK 45 nm Technology library. The simulation results show that the side-channel security metrics using KL divergence are 0.0204 for Montgomery and 0.0020 for the Arithmetic-style implementation. This means that Arithmetic-style implementation has better side-channel resistance than the Montgomery implementation. In addition, we evaluated the security of the AES encryption with RNS secure logic on a Spartan-6 FPGA Board. Experimental results show that the protected AES circuit offers 79% higher resistance compared to the unprotected AES circuit.

Volatile Memristor in Leaky Integrate-and-Fire Neurons: Circuit Simulation and Experimental Study

In this paper, circuit implementation of a leaky integrate-and-fire neuron model with a volatile memristor was proposed and simulated in the SPICE simulation environment. We demonstrate that simple leaky integrate-and-fire (LIF) neuron models composed of: volatile memristor, membrane capacitance and neuron resistance can mimic spatial and temporal integration, firing function and signal decay. The existing leaky term originates from the recovery of the initial resistive state in the memristor in the spontaneous reset cycle, which is essential for emulating the forgetting process in all-memristive neural networks (MNNs). Furthermore, a diffusive perovskite memristor was used to validate the model where intrinsic memristors’ capacitance acts as neuron membrane capacitance. Good agreement with experimental and simulation results was observed. Volatility, as an inherent property of specific memristors, eliminates the need for usage of an additional peripheral circuit which will reinitialize device state, thus allowing the development of energy-efficient, large scale complex memristive neural networks. The presented circuit level model of LIF neurons can facilitate the design of MNNs.

TMS-Crossbars With Tactile Sensing

The first stage of tactile sensing is data acquisition using tactile sensors and the sensed data is transmitted to the central unit for neuromorphic computing. The memristive crossbars were proposed to use as synapses in neuromorphic computing but device intelligence at the sensor level are not investigated in literature. We propose the concept of Transistor Memristor Sensor (TMS)-crossbar by including sensor to memristor crossbar array configuration in the input layer of the neural network architecture. 2 possible cell configurations of TMS crossbar arrays: 1 Transistor 1 Memristor 1 Sensor (1T1M1S) and 2 Transistor 1 Memristor 1 Sensor (2T1M1S) are presented. We verified the proposed TMS-crossbar in the practical design of analog neural networks based Braille character recognition system. The proposed design is verified with SPICE simulations using circuit equivalent of FLX-A501 force sensor, TiO$_2$ memristors and low power 22nm high-k CMOS transistors. The proposed analog neuromorphic computing system presents a scalable solution and is possible to encode 125 symbols with good accuracy in comparison with other Braille character recognition systems in the literature. The benefits of analog implementation of the TMS crossbar arrays is substantiated with results of accuracy, area and power requirements in comparison with the binary counterparts.

Measuring and Modeling Single Event Transients in 12-nm Inverters

In this article, we present a unique method of measuring single-event transient (SET) sensitivity in 12-nm FinFET technology. A test structure is presented that approximately measures the length of SETs using flip-flop shift registers with clock inputs driven by an inverter chain. The test structure was irradiated with ions at linear energy transfers (LETs) of 4.0, 5.6, 10.4, and 17.9 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg, and the cross sections of SET pulses measured down to 12.7 ps are presented. The experimental results are interpreted using a modeling methodology that combines TCAD and radiation effect simulations to capture the SET physics, and SPICE simulations to model the SETs in a circuit. The modeling shows that only ion strikes on the fin structure of the transistor would result in enough charge collected to produce SETs, while strikes in the subfin and substrate do not result in enough charge collected to produce measurable transients. Comparisons of the cumulative cross sections obtained from the experiment and from the simulations validate the modeling methodology presented.

Low power class-AB VCII with extended dynamic range

In this paper we present a novel CMOS second generation voltage conveyor (VCII) topology featuring a wide voltage swing both at the X terminal and at the Z terminal. The VCII consists of a regulated common gate configuration at the Y current input terminal and a class-AB complementary-MOS closed loop output voltage follower that ensures the voltage buffering action between the voltage input X and the voltage output Z terminals. Spice simulation results using AMS 0.35 μm with a ±0.9 V supply voltage are provided to demonstrate the validity of the proposed topology. With a total power consumption of 28 µW, the VCII achieves a voltage swing at the X terminal of ±0.8 V, whereas a ±0.72 V is achieved on the Z terminal. Simulation results for DC and AC voltage and current gains are given, as well as harmonic distortions and noise figures. A final comparison table is also presented, where the proposed VCII is compared with other solutions presented in the literature.