Spartan 3E Research Articles

Optimized design for controlling LED display matrix by an FPGA board

The very important objective of the digital designer when using discrete gates for implement a Boolean function is to keep the number of used gates to a minimum and win a memory space without lost the original information. In this sense, the Simplification is very important and could be achieved by a purely algebraic process, but it can be tedious when it arrived to a very large number of variables. In this paper we describe an automat solution based on finite state machine (FSM) for simplify and practically optimize the complex logical functions. This method is programmed and tested on a display system which is based on light emitting diodes (LED) matrix and programmable platform with Field Programmable Gate Array (FPGA). The module is implemented in Spartan 3E family XC3S500E FPGA board. Keywords : Display Board, FPGA, FSM, LED, LED-Driver, Logic Simplification, Multiplex.

FPGA BASED: DESIGN AND IMPLEMENTATION OF NOC TORUS TOPOLOGY

The fundamental unit of building a Network on Chip is the router , it directs the packets according to a routing algorithm to the desired host. In this paper ,a router is designed using VERILOG language and implemented on Spartan 3E FPGA with the help of Integrated software environment ( ISE10.1) . The utilization of the Spartan 3E resources is excellent ( for example the number of slices required doesn’t exceed 3%) .After that a (2×2) mesh topology and a (2x2) torus topology network is designed and implemented using FPGA . An example is applied on the designed Network on Chip (NoC) which validates the design successfully.

TD-AMS PROCESSING FOR VLSI IMPLEMENTATION OF LDPC DECODER

An Efficient analog to digital interface (TDC/DTC) is presented. In particular, we explore time-based techniques for data conversion, which can potentially achieve significant reductions in power consumption while keeping silicon chip area will be very small. On the basis of a generic mixed-signal system the scaling difficulties of analog and mixed-signal circuits based on a signal representation in the voltage domain are discussed for nanometer CMOS technologies. Easy to control and seamlessly embedded, were also low latency occur. Mainly applicant for LDPC implementation which is used for error correcting and image processing will be done. In gate level verilog hardware description language used for coding digital circuits using tool Xilinx ISE 10.1i and target family Spartan 3E,Device XC3S500, speed -5,package:FG320.The synthesized for the proposed digital circuits.

Pipelined Vedic-Array Multiplier Architecture

In this paper, pipelined Vedic-Array multiplier architecture is proposed. The most significant aspect of the proposed multiplier architecture method is that, the developed multiplier architecture is designed based on the Vedic and Array methods of multiplier architecture. The multiplier architecture is optimized in terms of multiplication and addition to achieve efficiency in terms of area, delay and power. This also gives chances for modular design where smaller block can be used to design the bigger one. So the design complexity gets reduced for inputs of larger number of bits and modularity gets increased. The proposed Vedic-Array multiplier is coded in Verilog, synthesized and simulated using EDA (Electronic Design Automation) tool - XilinxISE12.3, Spartan 3E, Speed Grade-4. Finally the results are compared with array and booth multiplier architectures. Proposed multiplier is better in terms of delay and area as compared to booth multiplier and array multiplier respectively. The proposed multiplier architecture can be used for high-speed requirements. Index Terms—Vedic, Array, Multiplier, Booth, High Speed.

Design of RNS Based Addition Subtraction and Multiplication Units

Residue number systems have gained significant importance in the field of high-speed digital signal processing due to their carry-free nature and speed-up provided by parallelism. The cynical aspect in the application of RNS is the selection of the moduli set and the design of the conversion units. In the residue number system, a set of moduli which are independent of each other is given. An integer is represented by the residue of each modulus and the arithmetic operations are based on the residues individually. The arithmetic operations based on residue number system can be performed on various moduli independently to avoid the carry obtained in addition, subtraction and multiplication, which is usually time consuming. Thus, the comparison and division are more complicated and the fraction number computation is immured. In this paper, work is done by the residues of the number and performed Addition, Subtraction and Multiplication are performed which shows more advantages of Carry Free nature. Performance of RNS based Addition, subtraction and Multiplication Units has been implemented for modulo set {2 n -1, 2 n , 2 n +1} for n=2,3 with the targeted device of Spartan 3E using hardware description language called Verilog and synthesized in Xilinx ISE 13.2.

REMOTE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) LAB

In today’s world, e-learning has proved to be a very useful technology. In addition to e-learning, e-labs are also being implemented. E-labs can be either virtual or remote. This paper is an initiative to create a remote fpga lab. The implementation of the same is also complete. The base kit used is the spartan 3E family of FPGA which is interfaced with an arduino board through a LabView interface for providing the input into the FPGA from the remote desktop. The outputs are displayed in the remote computer. The outputs can also be viewed through the webcam. The main intention of this project is to make distance learning easy. It is also an advantage for students as additional experiments that do not come under the syllabus can be performed anytime, anywhere.

A Novel 8 Bit Digital Comparator for 3x3 Fixed Kernel based Modified Shear Sorting

The need for an optimized area, speed and power plays a vital role for any median filter is good at removing impulse noise without degrading the image details. The main operation of the median is Rank ordering. It is a computationally complex operation, so it is hard to implement it in real time. This paper introduces a new sorting technique called for Snake like sorting. The proposed Sorting technique is implemented as a parallel architecture. This algorithm is a Mesh based sorting that require less number of comparators for rank ordering. The proposed architecture is compared with other Rank Ordering algorithm on the basis of power, speed, and area and found to exhibit good results. The proposed architecture is implemented on parallel and pipelined schemes and is targeted for Spartan 3e Device with gate capacity 5000 using Xilinx 7.1i compiler version. The pipelined scheme has an operating frequency of 81 Mhz occupying 283 slices with a gate count of 5,640.

Interfacing Force Sensor to on Board ADC of Spartan 3E

Force sensor from interlink that use square pad forforce sensing is useful for many applications, as the resolution of this sensor continues and FPGA is digital, an ADC is required to deal with such sensor and as the embedded ADC of Spartan 3E kit need complex signals synchronization to work.This paper present a hardware design and optimized implementation based VHDL coding of control unit that make the ADC of Spartan 3E kit operate in real time. The system use Moore states machine style for generating ADC synchronization signals. Also, the result observed via new approach, which is instead of using chip scope for displaying values of ADC, LabVIEW FPGA environment is used so it‟s possible to display result on PC via USB. The control is optimizedand efficient due to using only 1% of FPGA chip and the measured force can be displayed in real time and the proposed control unit can be work as standalone or coprocessor architecture. General Terms FPGA, VHDL, LabVIEW FPGA, Force, Sensor.

Design of Hard and Soft Decision Decoding Algorithms of LDPC

The demand for satellite communication and a wide-ranging objective, however, is often to achieve maximum data transfer, in a minimum bandwidth while maintaining an satisfactory quality of transmission. The transmission quality is basically concerned with the probability of bit error at the receiver here with respect to communication. This is an attempt to achieve highest capacity with minimum error rate by implementing modern codes named as LDPC(Low Density Parity Check codes) and it is represented here various decoding schema to decode and encode them At the present time LDPC codes has received a superior interest because their error correction performance and their functional world wide applications. The paper represents LDPC significance ,its characteristics and encoding and iterative decoding approaches to achieve channel capacity. Thus we need some technology that utilizes this available bandwidth by providing good error correction capability. We can also achieve it by using FPGA spartan 3e’s VHLD implementation. General Terms Iterative decoding, LDPC, encoding.

An AMBA Advanced High performance Bus Tracer with Real time Compression for Support of SoC

AMBA (Advanced Microcontroller based Bus Architecture) consists of AHB (Advanced High performance Bus), APB (Advanced Peripheral Bus), ASB (Advanced System Bus) and AXI (Advanced extensible Bus). This Paper proposes the debugging and analyses of system on chip (SoC) at various test conditions by verifying the functional aspects of the on-chip bus. Here we select an Advanced High performance bus (AHB), since the AHB bus signals are hard to examine as they are extremely embedded in the system on chip and there are no sufficient I/O pins to access these signals. Hence we embed a bus tracer in SoC to capture and compress the bus signals with different compression mechanisms. The tracer is successfully verified in FPGA SPARTAN 3E (XC3S500E). Tools used in this manuscript Modelsim for simulation and XILINX ISE II for RTL Synthesis.

Design and Implementation of Bpsk Modulator and Demodulator Using Vhdl

This paper give the brief description of digital communication system.Digital communication is more reliable, secure and efficient than that of analog communication.In Digital communication,BPSK is most important and efficient technique in terms of signal power. In this paper BPSK modulator and demodulator are purely design by using hardware description language (VHDL) and implementing it on Spartan 3E FPGA kit. I. Introduction In the last years, a major transition from analog to digital modulation techniques has occurred and it can be seen in all areas of wireless communication, satellite and cellular systems. A digital communication system is more reliable than an analog. The aim of the paper is to create a BPSK (Binary Phase Shift Keying) modulator and demodulator using Xilinx ISE 12.3 software. BPSK consist of modulator a channel and demodulator. The modulated signal was achieved in the first Spartan 3E board, passed through a channel and transmitted to the second board, which behaves as a demodulator.

FPGA Implementation of Viterbi Algorithm for Decoding of Convolution Codes

Abstract: Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data. Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder. Power reduction in Viterbi decoder could be achieved by reducing the number of states. A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed. Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN). It operates on data stream and has memory that uses previous bits to encode. The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code. The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register. A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems. It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN. The Viterbi decoder of Constraint length 7 and code rate 1⁄2 is considered. The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

Design of Parallel Prefix Adders using FPGAs

parallal prefix adders are one of the fastest types of adder that had been created and developed. this paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple ripple carry adder and carry skip adder.these designs of varied bit widths were Implemented on a xilinx spartan 3E FPGA and delay measurements were made with a high performance logic analyzer .Due to the presence of a fast carry-chain,the RCA design exhibit better delay performance up to 128 bits.the carry tree adders are expected to have a speed advantage over the the RCA as bit widths approach 256.

An FPGA Based Controller for a SOFC DC-DC Power System

Fuel cells are an attractive option for alternative power and of use in a variety of applications. This paper proposes a state space model for the solid oxide fuel cell (SOFC) based power system that comprises fuel cell, DC-DC buck converter, and load. In this investigation we have taken up a case study for SOFC feeding a DC load where a DC-DC buck converter acts as the interface between the load and the source. A proportional-integral (PI) controller is used in conjunction with pulse width modulation (PWM) that computes the pulse width and switches the MOSFET at the right instant so that the desired voltage is obtained. The proposed model is validated through extensive simulation using MATLAB/SIMULINK. Controller for the fuel cell power system (FCPS) is prototyped using XC3S500E development board containing a SPARTAN 3E Xilinx FPGA that simplifies the entire control circuit besides providing additional flexibility for further improvement. The results clearly indicate improved performance and validate our proposed model.

FPGA based Smart Wireless MIMO Control System

In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input & Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively.

Conception and Implementation of a BCH Code on a FPGA Board

In this paper we have designed and implemented a BCH (15, 7, 5) encoder on FPGA using VHDL description language and we implanted it on an FPGA Spartan 3E Starter board. The digital logic implementation of binary encoding of multiple error correcting BCH code of length n=15 is organized into shift register circuits. Multiple characteristics of cyclic codes will be discussed further on. The results of the simulation and implementation using Xilinx ISE.12.1 software and the LCD screen on the FPGAs Board will be shown at last.

An AHB on Chip Bus Tracer with Real Time Compression for SoC Support

This paper illustrates the system on chip (SoC) debugging and analyses its behavior at several test conditions by verifying the functional aspects of the on-chip bus. Here an Advanced High performance bus (AHB) is selected, since the AHB bus signals are difficult to observe as they are deeply embedded in the system on chip and these I/O pins to access these signals is not possible. Hence we embed a bus tracer in SoC to capture and compress the bus signals. The tracer is successfully verified in FPGA. In this manuscript the selected software is XILINX ISE software design environment for RTL synthesis and model-Sim simulation software to verify the timing diagrams of the AHB SoC modules designed. The FPGA used is SPARTAN 3E (XC3S500E).

FPGA IMPLEMENTATION OF (15,7) BCH ENCODER AND DECODER FOR TEXT MESSAGE

In a communication channel, noise and interferences are the two main sources of errors occur during th e transmission of the message. Thus, to get the error free communication error con trol codes are used. This paper discusses, FPGA imp lementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each chara cter in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and co rrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carri ed out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrar ily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. F inally both encoder and decoder design is implement ed on Spartan 3E FPGA.

Analysis and Design of E1 over Ethernet Gateway

The most commonly used technique in networking nowadays is packet switching. It has become one of the important infrastructure elements in the communication society. Time-division multiplexing (TDM) and Synchronous Digital Hierarchy (SDH) over Ethernet is regarded as an economical and efficient scheme in the mid-distance of TDM or (SDH) interconnections. This paper focus on the design and analysis of the E1 to Ethernet protocol converter (Gateway), it based on the frame granularity scheme which takes into account of miniaturization, power, cost and time delay of companding reduction. The E1 to new Ethernet (LAN) link protocol converter designed in this paper utilizes universal programmable devices. A new approach is proposed, modeled and then simulated by using (VHDL) code and implemented in Spartan 3E kit. In high speed networks, packet processing is relatively expensive while bandwidth is cheap. The proposed approach considers the most important factor affecting the performance of high speed networks. These are packet processing time, throughput, and packet efficiency. Packet processing time is an issue in real time communications. As consequences, real time signal quality (like the voice) might be degraded severely when the process time exceed its limits. In this paper, the simulation results show that the active mode of the frame payload effectively improves the performance of the Ethernet protocol. In E1 line, 36% bandwidth is saved at half traffic load of the maximum.

Hardware Testable Design of Genetic Algorithm for VLSI Circuits

Accurate and fast testing of digital circuits is very much essential in real time applications. Hardware analysis of digital circuits, which is otherwise very tedious and time consuming, is attempted using the artificial intelligence technique: Genetic Algorithms (GA). GA is used to find an input sequence to a digital circuit for testing, as it reduces the hardware utilization, complexity and computational time of the circuits. All the GA processes are simulated and implemented by using Xilinx 10.1 and SPARTAN 3E.