Spartan 3E Research Articles

Automatic Thresholding Technique Using Reconfigurable Hardware

This research presents an efficient automatic thresholding technique based on Otsu’s method that can be used in edge detection algorithms and then applied as a plug-in for real-time image processing devices. The proposed thresholding technique uses an iterative clustering based method that targets a reduced number of operations. It is well known that the Otsu calculates the global threshold splitting the image into two classes, foreground and background, and choose the threshold that minimizes the interclass variance of the threshold black and white pixels. In this paper, a faster version of Otsu’s method is proposed knowing that the only pixels that have to be moved from one class to another class are the ones with values in between the previous two thresholds. This procedure yields the same set of thresholds as the original method but the redundant computation has been removed and, in this way, only few operations are required. The proposed thresholding technique has been implemented in software using C# programing language and in reconfigurable hardware on a Spartan 3E XC3S500E FPGA board using VHDL. The results obtained, presented for different digital images, confirm that the proposed iterative thresholding algorithm and architecture on FPGA can achieve the requirements to be included in real-time image processing systems.

Modified Unsigned Multiplier Algorithm With Wallace Tree Technique

A Wallace tree technique using Modified Unsigned Multiplier is proposed in this paper and is designed at gate level using Verilog HDL. Synthesized for Xilinx Virtex 6 low power, Spartan 6, Spartan 3E FPGA device. The result shows an improvement in terms of speed and slices or area. Performance and Area of integrated circuits are a major concern for VLSI circuit designers. This paper aims at more reduction of the latency and area or the number of slices. Day to day advent of new technology in the fields of digital signal processing and communication, VLSI, there is a great demand for the high-speed processing and Efficient area reduction in the design. Index Terms—Wallace tree Technique, Unsigned Multiplier, VLSI.

Design and Interfacing of I2C Master with Register and LCD Slaves

One of the foremost, well-liked, less sophisticated Serial communication standards, I2C; a bus protocol familiarly meant for the exchange of information among the peripherals residing on the constant circuit card, houses two-wires i.e., data and clock for supporting duplex communication between multiple masters and slaves do considered as prominent and efficient in Data transmission. The present work emphasizes on the I2C controller designed for interfacing with slaves, a simple control register of I2C switches/card where the data is written or scan from, subsequently, I2C core implementation on Spartan 3E FPGA, where one of its on-chip peripheral, in this case LCD treated as a slave for performing data transactions. The entire module is designed in Verilog HDL, functional checking is accomplished with the ISIM 10.0b simulator, followed by the design synthesis using Xilinx ISE14.4 tool

Design & Verification of Serial Peripheral Interface (SPI) Protocol

SPI (Serial Peripheral Interface), which was introduced by the company Motorola, and it is a protocol for communication of serial synchronous about the communication among the master and slave device, which is also used to provide communiqué between microcontroller and many devices which are additional and similar to external Analog to the Digital Converters, Digital to Analog Converters, and EEPROMs. Now a days, communication protocols are at low end. There are two different Protocols: 1) Inter-I2C and 2) SPI. Both of these protocols are well designed for the communications between the Integrated Circuits for communication with On-Board Peripherals. SPI is most commonly used protocol for both intra-chip and inter-chip, and is used at low or medium speed of data-stream transfer. This paper introduces about the quality of SPI Interface Protocol with Single Master and Single Slave configuration, which involves 8-bit of the data transfer and all necessary incorporates features that required for modern applications such as ASIC or SOC (System on Chip). The SPI design is verified and implemented by using System Verilog to show their coverage code and their functional correctness, the entire RTL was written using Verilog for Synthesis and then the Verification architecture is written using System Verilog. The implementation is done using Spartan 3E.

Effective CU Design Based Implementation of a 64-Bit Processor for Signal Processing Applications

The aim of this paper is to design simple and Effective digital control unit for a 64-bit processor core. Proposed idea is implemented in Spartan-III FPGA Architecture. Control unit (CU) directs the operation of the processor to get results. The function of CU is to fetch their instructions, examining them and execute the programs stored in the memory and executing them one after another in Main Memory. The Central Processing Unit (CPU) is the combination of Arithmetic and Logic Unit (ALU) and CU. The CPU receives information from several different elements; they are memory, control path and data path. Control Unit is required to produce the control signals for operating data path at each clock cycle. CU generates instructions to the memory, arithmetic/logic unit and input and output devices. The proposed control unit simulated in Xilinx and implemented in Spartan 3E , achieved less delay compared to existing approaches

Fuzzy devices for cooling the cutting tool of the CNC machine implemented on FPGA

Heating of a cutting tool during the processing detail on CNC machine cause thermal deformations which reduce the quality of the machined surfaces. The authors propose to use Peltier thermoelement to control thermal deformations. The article presents two devices to control thermoelement based on a current generator and a field effect transistor. Both devices change the current signal transmitted to the thermoelement by using two fuzzy-logical models. We used FPGA Spartan 3E for increasing speed of fuzzy models and the both devices. Therefore, the main goal of the article is to increase the speed of information processing in fuzzy devices. We increased the speed of processing information by using singleton membership functions on the output of fuzzy models, optimizing and parallelizing the program code for calculating fuzzy operations and replacing the division operations by shifts. Time tests conducted at frequency of 200 MHz showed that the current was calculated to 380 ns, the voltage conversion was carried out to190 ns.

Enhanced 32-Bit Adder Implementation using Different Configurations of Adders

Adders play a essential role with in the digital signal process systems. The 32-bit configuration is commonly used in few computerized systems and processors. In this paper, detail study about the implementation of 32-bit adders like Ripple Carry Adder (RCA), Carry Select adder (CSLA) and Carry Increment adder (CINA) is done for various configurational full adders using VHDL. The outcomes are acquired by executing VHDL in Xilinx ISE 14.5 with speed grade -5 of Spartan 3E family device.

PID Controller With Fuzzy Inference System As Simple Feedback For Closed Loop Control Of Intravenous Anesthesia

Anesthesia is an imperative activity during operation. Anesthesiologist perceives patient’s physiology and adjusts the drug rate. Sometimes, it may go overdose or under-dose which is proscribed. This process is merely in need of an expertise which in turn, may not be available every time and everywhere. But we can store this expertise with the help of fuzzy inference system and utilize it to judge the depth of anesthesia. A genuine effort has been made to design a PID controller with fuzzy inference system as simple feedback to control intravenous anesthetic drug delivery. This paper demonstratesthe design and implementation of experts’ based system with PID controller and comparison of the same with open loop target controlled infusion and fuzzy inference system without a controller. The conclusion of this study is that the PID controller with fuzzy inference system as simple feedback gives fast response with no overshoot. Ultimate prototype is implemented on Xilinx’s Spartan 3E Field Programmable Gate Array.

Designing and Implementing FPGA for AES

The execution of DES and triple DES is not possible on hardware platform because they consume huge memory space. We can use field programmable gate arrays in order to do the hardware implementation because of its low charge, advertising space and reconfiguration nature. This paper aims at reducing the delay by using pipeline for speeding up the process. The proposed pipeline structure has a characteristic of having round keys which during iterations of encryption are utilized and an encryption method is used for generating them in parallel. The overall delay related to a delay of coding of plaintext block is reduced. The simulation is done in VHDL by Xilinx and implementation is done on FPGA Spartan 3E.

An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

A unique design for an optimized N-bit multiplier is proposed and implemented which utilizes a modified divide-and-conquer technique. The conventional technique requires four N/2-bit multipliers to perform N-bit multiplication, whereas the proposed design uses only one multiplier module in hardware to perform the functionality of four modules. It uses Dadda algorithm in its multiplier module. It has been implemented using Verilog HDL, and a good accuracy of results was observed in simulations which effectively verify its functionality. Design was also synthesized on various FPGAs including Spartan 3E, Virtex-5 and Virtex-7. Performance summary, after place and route, showed that the proposed approach significantly reduces hardware utilization. Furthermore, the proposed design is almost 75% more efficient in terms of resources utilization and operating frequency as compared to the conventional design.

Bandwidth Efficient Frame Structure Algorithm and Analysis: An Extension to Telemetry Standard

An onboard telemetry system has access to a limited wireless bandwidth due to a high-speed airborne vehicle and large channel changing characteristics. The inefficiency of data placement happens at the transmission end if there is a large deviation between the packet rate and the frame rate for serial channels. For one of the current examples, the data rate of the transmitted signal can be decreased from 22 Mbps by straightforward placement in the major frame and to 3 Mbps using the novel algorithm introduced in this paper. The mathematical model in the subject is termed the bandwidth-efficient frame structure algorithm. A Xilinx Spartan 3E series has been used to frame the acquired data at the transmitting end and to deframe at the receiving end. The Inter-Range Instrumentation Group 106 standard has been used for the frame structure.

Experimental Verification of Three phase quasi Switched Boost Inverter with an Improved PWM Control

<p>In this paper, an experimental investigation of a three phase quasi Switched Boost Inverter (qSBI) topology is proposed and analysed with an improved Pulse Width Modulation strategy. The qSBI is capable of providing both boost and inversion actions in a single stage. The improved PWM control technique can provide a higher boost with the reduced duty ratio. The theoretical analysis presented in this work is validated using an experimental set up of 100W qSBI topology and hardware results are shown for verification. The improved PWM strategy is implemented and firing pulses are generated in FPGA SPARTAN 3E kit. With the duty ratio of 0.05, the peak ac load voltage of 80 V is obtained. The performance of three phase qSBI is analysed with both conventional PWM strategy and improved PWM strategy. The observations are presentated in detail.</p>

FPGA Based Engine Control Module for Fuel Injection System

Fuel injection system is an indispensible part of the present day automobiles. The depletion of the fuels along with continuous surge in the fuel prices has made it imperative to use fuel economically and restricting the wastage to a minimum. Contrary to the carburetor, using predefined amount of fuel irrespective of the environment, Fuel Injection System uses just the required amount of fuel based on the operating conditions as sensed by the Engine Control Module (ECM). Numerous parameters are required to be sensed by the ECM to achieve optimum efficiency of the engine. To handle the processing of such large number of parameters, a robust architecture is required. This paper presents the design and implementation of ECM utilized in Electronic Fuel Injection (EFI) system on a Field Programmable Gate Array. The ECM architecture discussed in the proposed system is computationally efficient enough to fulfill ever-increasing functionalities of the ECM. The main objective of this research is to sense the parameters required for the ECM analysis and to interpret and analyze this data and accordingly control the solenoid (actuator). The CAN controller is also deployed in an FPGA to facilitate the communication between ECM and Human Machine Interface (HMI) to indicate the parameters sensed by the sensor on the LCD. The target device (FPGA) for this work is Xilinx Spartan 3E and the design tool is Xilinx ISE 14.7 with the ECM and CAN controller being modeled in Verilog Hardware Description Language (HDL).

FPGA Implementation of a Robust MPPT of a Photovoltaic System Using a Fuzzy Logic Controller Based on Incremental and Conductance Algorithm

Climate dependence requires robust control of the photovoltaic system. The current paper is divided in two main sections: the first part is dedicated to compare and evaluate the behaviors of three different maximum power point tracking (MPPT) techniques applied to photovoltaic energy systems, which are: incremental and conductance (IC), perturb and observe (P&O) and fuzzy logic controller (FLC) based on incremental and conductance. A model of a photovoltaic generator and DC/DC buck converter with different MPPT techniques is simulated and compared using Matlab/Simulink software. The comparison results show that the fuzzy controller is more effective in terms of response time, power loss and disturbances around the operating point. IC and P&O methods are effective but sensitive to high-frequency noise, less stable and present more oscillations around the PPM. In the second section, the FPGA platform is used to implement the proposed control. The FLC architecture is implemented on an FPGA Spartan 3E using the ISE Design Suite software. Simulation results showed the effectiveness of the proposed fuzzy logic controller.

An optimal low power digital controller for portable solar applications

The design of controllers for solar energy harvesting systems plays the key role in deciding the efficiency of the energy utilized. In applications of energy scavenging, the harvested power is consumed for about 70% in the operation of the converter and controller blocks before being supplied to the load. The proposed optimal Field Programmable Gate Array based Load Predictive Maximum Power Point Tracking (LP_MPPT) Digital Controller is used for low power, speedy, and decisive energy scavenging systems for a long run in applications of wireless or remote sensing or portable. LP_MPPT helps to predict the need of the load and generate the converter output as buck/boost/buck_boost mode power in comparison to the input from solar panels for every clock cycle. The power consumption of the controller section is comparatively reduced as the buck_boost mode of operation utilizes the no operation state. The proposed methodology is simulated and implemented using Xilinx ISE Design Suite 12.1 which is supported by the family SPARTAN 3E. The simulation results thus obtained show an increase in efficiency (94.3%) with trade off factors, namely, speed and area.

Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code

The Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It is one of the finest operation in the area of digital signal and image processing. FFT is a luxurious operation in terms of MAC. To achieve FFT calculation with a many points and with maximum number of samples the MACs requirement could not be matched by efficient hardware’s like DSP. A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. In this paper, we present the implementation of fast algorithms for the DFT for evaluating their performance. The performance of this algorithm by implementing them on the Xillinx 9.2i Spartan 3E FPGAs by developing our own FFT processor architecture.

FPGA implementation of DS-CDMA Transmitter and Receiver

Direct sequence spread Spectrum (DSSS) is also known as direct sequence code division multiplexing. In direct sequence spread spectrum the stream of information to be transmitted is divided into small pieces each of which is allocated across to a frequency channel across the spectrum. Data signal at the point of transmission is collaborated with a higher data-rate bit sequence (also called chipping code) that divides the data according to a spreading ratio. A redundant chipping code helps the signal resist interference and also enables the original data to be recovered if data bits are damaged during the transmitting. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented on SPARTAN 3E FPGA. The Xilinx synthesis technology (XST) of Xilinx ISE tool used for synthesis of transmitter and receiver on FPGA Spartan 3E.

Design and Implementation of FIR Filter Architecture Using High Level Transformation Techniques

Objectives: FIR filter structure is designed with area and delay optimization is designed using Systolic Architecture and Associativity High Level Transformation technique in this paper. Finite Impulse Response (FIR) filter structure with optimized parameters is one of the major challenges in VLSI Signal Processing. Methods/Statistical Analysis: The designed FIR filter is designed using Modelsim for functionality verification and the structure is implemented in Spartan 3E FPGA kit using Xilinx ISE simulator for the analysis of the designed architecture. Findings: The FIR filter is designed with 4-Tap, 8-Tap and 16-Tap length and the designed architecture using Systolic architecture with Associativity technique shows 8.9%, 2.3% and 2.4% reduction in LUT for 4-Tap,8-Tap and 16-Tap filter respectively and 14.22%,11.89% and 12.32% reduction in delay for 4-Tap,8-Tap and 16-Tap filter respectively. Application/Improvements: Further Associativity techniques may be used for future work. Keywords: Architecture, FIR Filter, High Level Transformation

Implementation of reconfigurable galois field multipliers over2m using primitive polynomials

The Galois field multiplier finds extensive use in cryptographic solutions and applications. The Galois field multiplier can be implemented as fixed bitwise or reconfigurable. For fixed length, the data is restricted to the fixed length. But in reconfigurable GF multipliers, the bit length of the multiplier is flexible and is independent of hardware architecture. This paper proposes a method to implement a reconfigurable GF multiplier for various bit values from 8 to 128 bits. This paper compares the area complexity of various bit size in Xilinx Spartan 3E family FPGA and estimates the resources required for the implementation.

FPGA implementation and analysis of model predictive current control for three-phase voltage source inverter

A detailed investigation of the model predictive current control (MPCC) for a three-phase voltage source inverter (VSI) with an output RL filter is examined in this manuscript. The investigation on VSI and its operating conditions such as dynamic, steady state, transient state condition with balanced and unbalanced loads are explained. The parameter variations such as sampling time, filter inductance and DC-link voltage variations are also explained in terms of load current Total Harmonic Distortion (THD) and inverter switching frequency. During each sampling period, the discrete mathematical model of the system is used to predict the load current for all the inverter switching state. These predictions are estimated using cost function, and so, the switching state which gives minimum cost function is selected and applied to the inverter. The effectiveness of the control technique is verified in MATLAB software and also in real-time hardware setup using Xilinx XCS500E Spartan 3E FPGA board. The detailed simulation and hardware results are included to investigate the implementation.