Abstract
Objectives: FIR filter structure is designed with area and delay optimization is designed using Systolic Architecture and Associativity High Level Transformation technique in this paper. Finite Impulse Response (FIR) filter structure with optimized parameters is one of the major challenges in VLSI Signal Processing. Methods/Statistical Analysis: The designed FIR filter is designed using Modelsim for functionality verification and the structure is implemented in Spartan 3E FPGA kit using Xilinx ISE simulator for the analysis of the designed architecture. Findings: The FIR filter is designed with 4-Tap, 8-Tap and 16-Tap length and the designed architecture using Systolic architecture with Associativity technique shows 8.9%, 2.3% and 2.4% reduction in LUT for 4-Tap,8-Tap and 16-Tap filter respectively and 14.22%,11.89% and 12.32% reduction in delay for 4-Tap,8-Tap and 16-Tap filter respectively. Application/Improvements: Further Associativity techniques may be used for future work. Keywords: Architecture, FIR Filter, High Level Transformation
Highlights
The importance of reducing area and delay parameters is increasing as range of sophistication of applications in Very Large Scale Integration (VLSI)
In that way many techniques has been incorporated for the reduction of power which can be done by reducing the number of functional units in the architecture and to increase the speed of the system by reducing the critical path of the circuit through various methods[1]
The critical path of the proposed architecture is given by Tmult + Tadd
Summary
The importance of reducing area and delay parameters is increasing as range of sophistication of applications in Very Large Scale Integration (VLSI). The three important parameters to be considered for any VLSI architecture designs are Area, Power and Delay. In that way many techniques has been incorporated for the reduction of power which can be done by reducing the number of functional units in the architecture and to increase the speed of the system by reducing the critical path of the circuit through various methods[1]. The FIR filter is considered here where a High level transformation technique has been incorporated for the reduction of area and to improve the speed of the system. The designed FIR filter can be used in many VLSI applications such as Adaptive Noise Cancellation and System Identification techniques applications
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