FPGA IMPLEMENTATION OF (15,7) BCH ENCODER AND DECODER FOR TEXT MESSAGE

Abstract

In a communication channel, noise and interferences are the two main sources of errors occur during th e transmission of the message. Thus, to get the error free communication error con trol codes are used. This paper discusses, FPGA imp lementation of (15, 7) BCH Encoder and Decoder for text message using Verilog Hardware Description Language. Initially each chara cter in a text message is converted into binary data of 7 bits. These 7 bits are encoded into 15 bit codeword using (15, 7) BCH encoder. If any 2 bit error in any position of 15 bit codeword, is detected and co rrected. This corrected data is converted back into an ASCII character. The decoder is implemented using the Peterson algorithm and Chine’s search algorithm. Simulation was carri ed out by using Xilinx 12.1 ISE simulator, and verified results for an arbitrar ily chosen message data. Synthesis was successfully done by using the RTL compiler, power and area is estimated for 180nm Technology. F inally both encoder and decoder design is implement ed on Spartan 3E FPGA.