Spartan 3E Research Articles

FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively.

The application of Verilog in the development of casual games

Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and intelligence in modern society. As digital technology continues to advance across various industries, the need for effective and dependable digital circuit design languages is also increasing. This paper delves into the complex process of recreating the timeless arcade classic Pac-Man on the Spartan 3E FPGA platform using hardware description and digital circuit techniques and the Verilog programming language. Through a comprehensive review of existing literature and research, this study investigates the fusion of traditional game design principles with state-of-the-art hardware programming methods, demonstrating the seamless integration of software-driven game mechanics with hardware-based implementation. Through careful design and coding strategies, Pac-Man's basic functionality, such as maze traversal, ghost AI, and pellet consumption, is faithfully replicated using Verilog modules customized for the Spartan 3E FPGA board. By bridging the realms of game development and hardware engineering, this paper not only showcases the versatility of Field Programmable Gate Array (FPGA) technology in entertainment applications but also underscores the interdisciplinary nature of modern computing endeavours.

FPGA based Flexible Implementation of Light Weight Inference on Deep Convolutional Neural Networks

Standard Convolution (StdConv) is the main technique used in the state of the art Deep Convolutional Neural Networks (DCNNs). Fewer computations are achieved if Depthwise Separable Convolution technique (SepConv) is used as an alternative. A crucial issue in many applications like smart cameras and autonomous vehicles where low latency is essential stems from deploying a lightweight and low cost inference models. An acceptable accuracy should be kept with tolerable computations and memory access load. A flexible architecture for different DCNN convolution types and models is proposed. The flexibility comes from the sharing of one memory access unit with different types of layers regardless of the selected kernel size, by multiplying each weight vector by local operators with variant aperture. Moreover, one depthwise computation unit can be used for both standard and pointwise layers. The learnable parameters are quantized to 8-bits fixed point representation and that gives very limited reduction of accuracy and a considerable reduction of the Field-Programmable Gate Array (FPGA) resources. To reduce processing time, inter layer parallel computations are performed. The experiment is conducted by using grey scale ORL database with shallow Convolutional Neural Network (CNN) and the colored Canadian Institute for Advanced Research 10 classes (CIFAR-10) database with DCNN, and a comparable accuracies of 93% and 85.7% are achieved respectively using very low cost of Spartan 3E and moderate cost of zynq FPGA platforms

Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches

The multilevel inverter (MLI) has been developed as a powerful power conversion scheme for several processes, including renewable energy, transmission systems, and electric drives. It has become popular across medium- to high-power operations due to its many advantages, including minimum harmonic content, low switching losses, and reduced electromagnetic interference (EMI). In this paper, the capacitor voltage balancing technique-based pulse width modulation (PWM) has been proposed. The proposed PWM strategy offers several advantages, such as high-quality output waveforms with reduced harmonic distortion, improved efficiency, and better control over the output voltage. The Xilinx ISE 10.1 software was used for synthesizing, and the VHDL code was written for the proposed method. MATLAB software was used to simulate and hardware was used to verify the proposed system. The SPARTAN 3E FPGA was used for the generation of the PWM. This paper developed a 2 kW single-phase 15-level inverter that created an AC wave from the DC input voltage, with a total harmonic distortion (THD) of 8.02%, which was less than the THD achieved from other conventional MLI. The results indicate that MLI topologies with low total harmonic currents, fewer switches, and higher output voltage levels are better stabilized during load disturbance circumstances.

A Novel Implementation of QPSK Modulator on FPGA

QPSK is one of the digital modulation techniques in communication system that has wide applications in the field of wireless, satellite communication, Bluetooth, OFDM etc. The Conventional QPSK modulators designs are generally based on IQ approach. In these modulators multipliers are used to separate the modulating signal into the in-phase and quadrature phase which increases the hardware complexity. The objective of this work is to implement the digital QPSK modulator with conventional and another approach of digitization. In this approach a digitized carrier wave is generated and QPSK phase shifting is provided by 4:1 multiplexer according to the data bits. The implementations of both the designs are done on Spartan 3E Xilinx FPGA through the verilog hardware description language. The QPSK modulator based on the Digitized approach is simpler in terms of hardware circuitry.

Parallel Hardware Implementation of Walsh Hadamard Transform

The Walsh Hadamard Transform is a powerful notion in digital signal processing. This paper explains the construction of parallel hardware architecture using the mathematical concept of Kronecker product based approach to Walsh Hadamard Transform and its simulation using Verilog. This architecture is simulated here using Field Programmable Gate Array (FPGA) technology in Verilog Spartan 3e platform. Furthermore, this paper illustrates the fast algorithm and parallel computational result of both one-dimensional and two-dimensional transforms using the Kronecker product.This algorithm can be used to implement a systolic array based dedicated hardware for computation of the transform. Our proposed hardware design for the Walsh Hadamard Transform will be used in various digital signal processing applications. The systematic derivation of parallel architecture design using the concept of Kronecker product and stride permutation would depict the real time processing rather than conventional way and reducing time complexity using minimal resources is a challenging task.

VLSI Design and Implementation of Multipliers for DSP Applications

A multiplier is a critical building block found in processors, embedded systems, VLSI applications, application specific integrated circuits, and most DSP applications. Speed, area, and power are the three primary thrust characteristics in VLSI design. Low power and high speed is the desirable characteristic in many applications that can extend the battery's life expectancy and increase the frequency of operation. The goal of this project is to design, implement and analyse the performance of array multipliers, booth multipliers, Wallace tree multipliers, and modified booth multipliers. In this work multipliers with different bit widths are implemented on Spartan 3E FPGA and their performances are analysed. Among these architectures Wallace tree multiplier provides higher speed of operation and consumes lesser power.

FPGA Implementation of Adaptive Sampling Algorithm for Space Applications

Adaptive sampling is a signal processing technique used in various aerospace applications. Many adaptive algorithms used for instrumentation and telemetry systems process the signal in the frequency domain, which leads to high computational cost and power. ASA-m solves this problem by performing all operations in the time domain. It estimated the subsequent sampling frequency to collect meaningful information based on mean velocity prediction. This novel algorithm is implemented on the Spartan 3E FPGA board to study the device power and hardware utilization for real-time vibration signal datasets. The significant recovery of data with a lesser number of samples and lower hardware utilization for the state of art algorithm ASA-m is brought out in this paper.

Analysis and Design of CRC-32 IEEE 802.3 Generator for 8 Bit Data Using VHDL

In the communication system to achieve better quality data transmission required a method that can detect errors and correct errors. Cyclic Redundancy Check (CRC) is one of the methods used to perform data transmission on data link layer that can detect errors. CRC-32 is used to error-checking on Ethernet or implemented to IEEE 802.3. CRC generator in this research use CRC-32 IEEE 802.3 with 8 bit data width. This research can be implemented in the field of Electrical Engineering, especially in the telecommunications section, namely Ethernet which functions for transfer files and data via a computer network. CRC here has a role to prevent data changes caused by noise during the transmission process. The methods used in this design is modulo-2 division parallel circuit. This design is expected to use a simple schematic circuit, less noise and less resources. Testing is done by matching result of simulation using Xilinx ISE Simulator with implementation on Spartan 3E XC3S500E device with result of count . This research requires a resource of 223 4-input LUTs, 114 Occupied slice, 72 IOB flip flops, 114 bonded IOBs and 1 BUFGMUXs, where this research obtained resources is fewer than with previous research

Performance Analysis of Low Power Interference Cancellation Architecture for OFDM System

Orthogonal Frequency Division Multiplexing (OFDM) is a wireless communication technology that is used for highly reliable and high data rate communication. In a multi-user OFDM system, the interference has occurred in the receiver side between the consecutive OFDM symbols. This interference reduces the performance of the OFDM system. To achieve good quality in received symbols the interference level should be minimized. The conventional cancellation system requires higher interference reduction time and power. These limitations of the conventional interference cancellation architectures for OFDM systems are overcome by proposing efficient and low power interference cancellation architecture. Hence, this paper proposes a novel and efficient architecture based on logic gates for interference cancellation in multi-user OFDM systems. The proposed design consist of multiplexers, inverters and OR gate. The heuristic parameters for the proposed cancellation architecture are computed by performing an XOR operation. Compared to existing architecture, the proposed interference cancellation architecture consumes 7 mW of power consumption in the Virtex processor, 33.59 mW of power consumption in Spartan 3E processor and 0.029 mW of power consumption in the CPLD processor. This proposed interference cancellation architecture consumes fewer hardware resources and consumes low power. The proposed system is designed using Verilog High Definition Language (HDL) and synthesized in Xilinx Project Navigator 12.1i. Further, this paper also proposes gate diffusion input (GDI) based implementation of proposed interference cancellation architecture to analyse a delay and power consumption compared to other logic style implementation.

Implementing Time-triggered Communication for Embedded Ethernet Real-time Network using IEEE 1588 Time Synchronization

A time-triggered embedded system has become a ubiquitous technique in safety-critical systems, such as automotive, aerospace, and medical sectors. Thus, precision is of utmost importance to determine if the application is synchronized correctly. The Network Time Protocol is the traditional protocol used for clock synchronization in wired networks. On the other hand, the protocol lacks hardware timestamping features, and it collects many timestamping errors because of the diversification of the queuing time in the switches and router. This drawback was implemented into a new protocol, and new features on the Precision Time Protocol, known as IEEE 1588-2008, were added. This paper proposes a real-time network for a time-triggered Embedded system, the Precision Time Protocol synchronize, on a Spartan 3E Field Programmable Gate Array (FPGA). Two approaches were also introduced to evaluate the performance using Precision Time Protocol: hardware and software implementations. MATLAB Simulink software was used to evaluate the software approaches. The result showed that the Precision Time Protocol used 0.83μs to complete the clock synchronization compared to the 4.65μs used by the Network Time Protocol, which was six times faster.

Performance Analysis of Clock Gated Coordinate Rotation Digital Computer Based Least Mean Square Filter Design for Video Processing Applications

Design of a low power FIR filter has always been an area of intense research concern. Application of Co-ordinate Rotation digital computer (CORDIC) algorithm for designing a low power FIR filter is presented in this paper. CORDIC algorithm helps in the computation of complex trigonometric functions by using shift and adds mechanisms avoiding the need for a separate processor in hardware implementation. The challenge of noise interruption in real time video signal capturing is rejected greatly by using CORDIC LMS filter architecture. Also the area, power, and delay of the LMS filter are reduced to a good extent because of CORDIC multipliers. When compared to the previously discussed filter techniques in various works, the proposed technique shows 21.13% reduction in delay and 90.28% decrease in leakage power. Further improvement in dynamic power savings is obtained through clock gating technique applied to the sequential elements in the circuit, which reduces dynamic power dissipation by 70% from the previous works. The comparative study of benchmark filters with their specifications is presented with a detailed analysis of area, delay, leakage, and dynamic power. The video processing using CORDIC LMS filter is verified with MATLAB R 2021A software. The hardware implementation of the proposed architecture is done on a SPARTAN 3E FPGA kit with Xilinx ISE design suite interface. The design is also verified for delay, area, leakage, and dynamic power using CADENCE with GPDK 180 nm library.

Design of High Speed and Low Area Confined Multiplier on FPGA

In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

A Comparative Study of Ring Oscillator PUFs Implementation on Different FPGA Families

Physical Unclonable Function (PUF) is an irreversible function that utilizes the process variation which occurs during silicon chip fabrication. The process variation is uncontrollable; thus, it cannot be modeled and is unique for each chip. Ring Oscillator PUF (ROPUF) has been used in the past to enhance the physical security of FPGAs by generating unique IDs which exploit the process variation introduced during the manufacturing process of the FPGA. In this paper, we describe the implementation and analysis of ROPUF on two different Xilinx FPGA families using 28 nm (Artix-7) and 90 nm (Spartan 3E) technologies. In each case, the ROPUF design is evaluated in terms of five parameters, namely, uniqueness, reliability, uniformity, bit aliasing, and diverseness. The reliability is measured based on responses generated from ROPUF at various temperature and voltage settings. The accelerated aging experiment results are also presented in the reliability evaluation. Our results show that the Artix-7 family yields the best results for uniqueness (45.15%) and diverseness (3.88). Based on the experimental results obtained, we suggest the scheme to increase the ROPUF’s reliability on both Spartan 3E and Artix-7 FPGAs by selecting ROs comparison pairs that have high frequency difference. We showed that the ROPUFs security is not been compromised by applying the scheme.

Physical design and verification of 3D reversible ALU by QCA technology

The “Quantum Dot Cellular Automata” or QCA is mainly used to design and simulate ‘3D’ structures for area-occupation, latency and total power reduction of any electronic circuit. At present, this “Nano-technology world” requires less-complex, small-size, high-frequency, fault-tolerant, low-power devices to increase the component-density in a single die. QCA designs are the well-known and optimum alternative of CMOS designs due to its above mentioned advantages. Further, reversible gates can also be formed based on QCA design. Reversible logic not only reduce the complexity of the design but also it can increase the information storage possibility by saving the power and energy. It is capable of reducing the leakage power (‘KTln2’ amount of dissipated energy for every bit can be ignored due to this logic). Cost of any device depends on the delay, power and occupied-area of the device which can be decreased by reversible multilayer (‘3D’) QCA structures. So, this proposed technique has an ability to provide the design for a cost-effective electronic device with good scalability and fault-tolerance. In the present work, we have simulated of an “Arithmetic and Logic Unit” in “QCA Designer” and “Xilinx” software. The first software is used due to the above advantages and here we apply reversible logic (reversible TSG gate with reversible AND-OR gate). This ALU is capable of performing one arithmetic (addition of two inputs) and three logical operations (AND, OR and XOR operations of two inputs) at a time. The TSG gate is used here as a full-adder with two input XOR operation and The reversible AND-OR gate is utilized for getting the AND result and OR result of two inputs. This design is also required a “4:1 MUX” which helps to select the operations properly. Schematic designs of proposed design with calculated values of delay and total power (for different room-temperature) are achieved in our work by using ‘Xilinx’ simulator. The used Verilog coding of our formed-design is also implemented in a “FPGA Board” (“Spartan 3E”) for hardware verification. Our presented circuitry can also continue its functionalities at high-temperature.

FPGA-Based Controller for a Hybrid Grid-Connected PV/Wind/Battery Power System with AC Load

The development and optimization of a hybrid system composed of photovoltaic panels, wind turbines, converters, and batteries connected to the grid, is first presented. To generate the maximum power, two maximum power point tracker controllers based on fuzzy logic are required and a battery controller is used for the regulation of the DC voltage. When the power source varies, a high-voltage supply is incorporated (high gain DC-DC converter controlled by fuzzy logic) to boost the 24 V provided by the DC bus to the inverter voltage of about 400 V and to reduce energy losses to maximize the system performance. The inverter and the LCL filter allow for the integration of this hybrid system with AC loads and the grid. Moreover, a hardware solution for the field programmable gate arrays-based implementation of the controllers is proposed. The combination of these controllers was synthesized using the Integrated Synthesis Environment Design Suite software (Version: 14.7, City: Tunis, Country: Tunisia) and was successfully implemented on Field Programmable Gate Arrays Spartan 3E. The innovative design provides a suitable architecture based on power converters and control strategies that are dedicated to the proposed hybrid system to ensure system reliability. This implementation can provide a high level of flexibility that can facilitate the upgrade of a control system by simply updating or modifying the proposed algorithm running on the field programmable gate arrays board. The simulation results, using Matlab/Simulink (Version: 2016b, City: Tunis, Country: Tunisia, verify the efficiency of the proposed solution when the environmental conditions change. This study focused on the development and optimization of an electrical system control strategy to manage the produced energy and to coordinate the performance of the hybrid energy system. The paper proposes a combined photovoltaic and wind energy system, supported by a battery acting as an energy storage system. In addition, a bi-directional converter charges/discharges the battery, while a high-voltage gain converter connects them to the DC bus. The use of a battery is useful to compensate for the mismatch between the power demanded by the load and the power generated by the hybrid energy systems. The proposed field programmable gate arrays (FPGA)-based controllers ensure a fast time response by making control executable in real time.

Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach

With the advancement in technology, various designs of multipliers offering low power consumption, high speed and less area have been proposed by many researchers. The main concern of electronic system designers is the energy minimization with the minimum penalty in speed and area for designing portable devices. Recent development focuses on the design of low-power multiplier for applications like biomedical signal processing requiring the least power consumption and delay-tolerant multiplier. This paper proposes a power-efficient design of the Wallace tree multiplier using a power-efficient 7:3 counter consisting of multiplexer and ex-or gates. The maximum power of the multiplier is consumed in the partial product tree reduction, and hence, in the proposed counter-based modular Wallace tree (CBMW) multiplier partial products are reduced using sequential 7:3 counter and the multi-bit addition in a single column reduces the complexity of the multiplier due to improvement in the locality. These proposed changes make design low power and scalable. The hardware utilization is minimum when a single 7:3 counter is used in partial product tree reduction per stage. The proposed multiplier is implemented in the Xilinx ISE design suite 14.7 using Verilog language on Spartan 3E FPGA. The design is also synthesized in Synopsys Design Compiler using 180 nm CMOS technology cell library. The corner analysis of the proposed design is performed in Synopsys PrimeTime, and the design meets all timing specifications. Also, the multiply and accumulate (MAC) unit is designed using the proposed multiplier to demonstrate an application of it. The detailed comparison is performed for 8-bit as well as 16-bit operands, and it shows that the CBMW multiplier gives better delay performance and consumes the least power compared to existing multipliers. It is proved to be an efficient multiplier in terms of Power-Delay Product (PDP). The power consumption of the proposed 16 $$\times $$ 16 multiplier is 88.16 mW and 87.7 $$\mu $$ W for Spartan 3E FPGA and ASIC design for 180 nm technology, respectively. It provides a promising performance for FPGA as well as for the ASIC platform.

Design of digital pulse width modulator architecture with digital PID controller for DC-DC converter using FPGA

A digital pulse width modulation architecture (DPWM) along with digital proportional integral derivative (PID) controller to control the DC-DC converter is presented in this paper. Difference between the actual output voltage and the reference voltage is calculated as error value. The look up table is created for PID controller to store the duty cycle ratio and the error value of power converters. Multipliers used in conventional algorithms are replaced by look up tables in the proposed work that enable the compact and low power implementation of digital controllers. DPWM architecture is developed with gray logic against the binary logic used in traditional DPWM architectures. Usage of gray counter also leads to low power consumption in the DPWM architecture. The proposed architecture is designed using Verilog hardware language and realized using field programmable gate array. PWM signals with varying duty cycle percentage can be derived from the proposed architecture. The generated PWM signal can control the switching condition of power converter to regulate the output voltage. Duty cycle percentage ranging from 16 to 96% can be developed with the proposed architecture. Simulation and experimental results of the architecture validate the proposed architecture. PWM signal with maximum operating frequency of 59.49 MHz and 60.22 MHz for SPARTAN 3A and SPARTAN 3E respectively can be generated with the proposed architecture.

A Novel Macroblock-Level Filtering Upsampling Architecture for H.264/AVC Scalable Extension

The scalable extension of the H.264/AVC standard, also called H.264/AVC SVC standard or simply SVC standard uses spatial upsampling in the spatial scalability modes. This work presents a novel upsampling architecture designed for operation at macroblock level and dyadic upsampling ratio with QVGA as the base layer resolution and VGA as the enhancement resolution.The adoption of a macroblock-level solution translates into a more efficient use of hardware resources with savings of approximately 25% in the number of ALUTs and DLRs and using about two hundred times less memory bits, when compared to previously published works. The designed architecture was synthesized targeting four FPGAs: Altera Cyclone III and Stratix IV and Xilinx Spartan 3E and Virtex 4. The best throughput was reached by the Xilinx Virtex 4 device, with a processing rate of 506 VGA frames per second. The worst result was reached by the Xilinx Spartan 3E FPGA, with 249 VGA frames per second. All target FPGAs surpasses the necessary throughput to decode VGA videos in real time. This very high throughput is important especially when low power applications are considered, since with low operation frequencies (9.34MHz) it is possible to reach real time (30 frames per second) for all target FPGAs.

FPGA Based Vehicle to Vehicle Communication in Spartan 3E

This paper presents economic and reconfigurable RF based wireless communication at 2.4 GHz between two vehicles. It implements digital VLSI using two Spartan 3E FPGAs, where one vehicle receives the information of another vehicle and shares its own information to another vehicle. The information includes vehicle’s speed, location, heading and its operation, such as braking status and turning status. It implements autonomous vehicle technology. In this work, FPGA is used as central signal processing unit which is interfaced with two microcontrollers (ATmega328P). Microcontroller-1 is interfaced with compass module, GPS module, DF Player mini and nRF24L01 module. This microcontroller determines the relative position and the relative heading as seen from one vehicle to another. Microcontroller-2 is used to measure the speed of vehicle digitally. The resulting data from these microcontrollers are transmitted separately and serially through UART interface to FPGA. At FPGA, different signal processing such as speed comparison, turn comparison, distance range measurement and vehicle operation processing, are carried out to generate the voice announcement command, warning signals, event signals, and such outputs are utilized to warn drivers about potential accidents and prevent crashes before event happens.