Design of digital pulse width modulator architecture with digital PID controller for DC-DC converter using FPGA

Abstract

A digital pulse width modulation architecture (DPWM) along with digital proportional integral derivative (PID) controller to control the DC-DC converter is presented in this paper. Difference between the actual output voltage and the reference voltage is calculated as error value. The look up table is created for PID controller to store the duty cycle ratio and the error value of power converters. Multipliers used in conventional algorithms are replaced by look up tables in the proposed work that enable the compact and low power implementation of digital controllers. DPWM architecture is developed with gray logic against the binary logic used in traditional DPWM architectures. Usage of gray counter also leads to low power consumption in the DPWM architecture. The proposed architecture is designed using Verilog hardware language and realized using field programmable gate array. PWM signals with varying duty cycle percentage can be derived from the proposed architecture. The generated PWM signal can control the switching condition of power converter to regulate the output voltage. Duty cycle percentage ranging from 16 to 96% can be developed with the proposed architecture. Simulation and experimental results of the architecture validate the proposed architecture. PWM signal with maximum operating frequency of 59.49 MHz and 60.22 MHz for SPARTAN 3A and SPARTAN 3E respectively can be generated with the proposed architecture.