Performance Analysis of Clock Gated Coordinate Rotation Digital Computer Based Least Mean Square Filter Design for Video Processing Applications

Abstract

Design of a low power FIR filter has always been an area of intense research concern. Application of Co-ordinate Rotation digital computer (CORDIC) algorithm for designing a low power FIR filter is presented in this paper. CORDIC algorithm helps in the computation of complex trigonometric functions by using shift and adds mechanisms avoiding the need for a separate processor in hardware implementation. The challenge of noise interruption in real time video signal capturing is rejected greatly by using CORDIC LMS filter architecture. Also the area, power, and delay of the LMS filter are reduced to a good extent because of CORDIC multipliers. When compared to the previously discussed filter techniques in various works, the proposed technique shows 21.13% reduction in delay and 90.28% decrease in leakage power. Further improvement in dynamic power savings is obtained through clock gating technique applied to the sequential elements in the circuit, which reduces dynamic power dissipation by 70% from the previous works. The comparative study of benchmark filters with their specifications is presented with a detailed analysis of area, delay, leakage, and dynamic power. The video processing using CORDIC LMS filter is verified with MATLAB R 2021A software. The hardware implementation of the proposed architecture is done on a SPARTAN 3E FPGA kit with Xilinx ISE design suite interface. The design is also verified for delay, area, leakage, and dynamic power using CADENCE with GPDK 180 nm library.