Spartan-6 Field Programmable Gate Array Research Articles

Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications.

The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range.

AN EFFECTIVE APPROACH OF BILATERAL FILTER IMPLEMENTATION IN SPARTAN-3 FIELD PROGRAMMABLE GATE ARRAY

This paper presents the Field Programmable Gate Array (FPGA) implementation of Bilateral Filter, in order to achieve high performance and low power consumption. Bilateral filtering is a technique to smooth images while preserving edges by means of a nonlinear combination of nearby image values. This method is nonlinear, local, and simple. We give an idea that bilateral filtering can be accelerated by bilateral grid scheme that enables fast edge-aware image processing. Nowadays, most of the applications require real time hardware systems with large computing potentiality for which fast and dedicated Very Large Scale Integration (VLSI) architecture appears to be the best possible solution. While it ensures high resource utilization, that too in cost effective platforms like FPGA, designing such architecture does offers some flexibilities like speeding up the computation by adapting more pipelined structures and parallel processing possibilities of reduced memory consumptions. Here we have developed an effective approach of bilateral filter implementation in Spartan-3 FPGA.

Implementation of XOR Based Pad Generation Mutual Authentication Protocol for RF Link

In RF link, without security the messages exchange between the two devices are monitoring by an eavesdropper. So the exclusive-OR (XOR) based pad generation protocol is used to safely transfer the data to the other point with necessary security and it maintaining confidentiality. This protocol produce the cover coding pad to mask the access password before the datas are transmitted. A specially designed pad generation will be implemented in digital domain to solve the insecurity problem in data communication RF link. This protocol developed under regulation of ISO 18000 - 6 type C protocol also known as EPC C1G2 RFID protocol. The linear feed back shift register (LFSR) generate the pseudo random binary sequence (PRBS) and it is used as data source to the pad generation function. The Xilinx 13.x software is used for synthesize and modelsim SE6.0 is used for simulating the result. The pad generation algorithm has been implemented in FPGA Spartan 3 PQ208-4 board to verify the result. Keywords- Field-programmable gate array (FPGA) implementation, mutual authentication, RF link, security, Zigbee.

Digital Implementation of Fuzzy Logic Controller for Real Time Position Control Applications

Fuzzy Logic Controller (FLC) systems have emerged as one of the most promising areas for Industrial Applications. The highly growth of fuzzy logic applications led to the need of finding efficient way to hardware implementation. Field Programmable Gate Array (FPGA) is the most important tool for hardware implementation due to low consumption of energy, high speed of operation and large capacity of data storage. In this paper, instead of an introduction to fuzzy logic control methodology, we have demonstrated the implementation of a FLC through the use of the Very high speed integrated circuits Hardware Description Language (VHDL) code. FLC is designed for position control of BLDC Motor. VHDL has been used to develop FLC on FPGA. A Mamdani type FLC structure has been used to obtain the controller output. The controller algorithm developed synthesized, simulated and implemented on FPGA Spartan 3E board.

An FPGA Chip Identification Generator Using Configurable Ring Oscillators

Physically unclonable functions (PUF) are commonly used in applications such as hardware security and intellectual property protection. Various PUF implementation techniques have been proposed to translate chip-specific variations into a unique binary string. It is difficult to maintain repeatability of chip ID generation, especially over a wide range of operating conditions. To address this problem, we propose utilizing configurable ring oscillators and an orthogonal re-initialization scheme to improve repeatability. An implementation on a Xilinx Spartan-3e field-programmable gate array was tested on nine different chips. Experimental results show that the bit flip rate is reduced from 1.5% to approximately 0 at a fixed supply voltage and room temperature. Over a 20 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C-80 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C temperature range and 25% variation in supply voltage, the bit flip rate is reduced from 1.56% to 3.125×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> .

Digital Control of Static Var Compensator with Field Programmable Gate Array

This paper is about real time simulation and implementation of FPGA Digital Control of Static VAR compensator for 750km lab model of artificial transmission line. In this paper, a new method of controlling SVC using Field Programmable Gate Array (FPGA) is suggested. FPGA controller is used to generate the firing pulses required to for Static Var Compensator. Pulses are synchronized with AC input; the delay of pulses determines the firing angle to driver circuit. The proposed control scheme has been realized using XILINX FPGA SPARTAN 2 XC2S200 and tested actual testing proves that these devices when installed, they keep the bus voltage same as reference voltage (sending-end voltage). The results are prominent and give a way for real-time implementation of the proposed control schemes. These control schemes are simulated for the real-time control along with real-time modeling and simulations.The results are prominent and give a way for real-time implementation

Fine grain faults diagnosis of FPGA interconnect

This paper proposes a new fine grain fault diagnosis method for the interconnect of an arbitrary design implemented in a Field Programmable Gate Array (FPGA). In the proposed method, interconnect faults detected at the primary output are back-tracked until the faulty nets are precisely located. This is carried out by programming the LUTs on the faulty path to be transparent and thus propagating the value of a specific net under test to the primary output for verification against the expected value of the net. After every back-tracking iteration, the fault location is narrowed down and thus the number of nets to be tested decreases significantly. Therefore, the upper bound of the number of configurations (NMAX) required to locate a faulty net, depends on the maximum combinational depth (DCOMB) of the circuit, and it is approximately equivalent to three times of DCOMB. The proposed method has the ability to locate multiple faults without any fault masking with fault coverage that includes all possible stuck-at, open and pair-wise bridging faults. The proposed method is validated on the ISCAS’89 benchmark circuits mapped on Xilinx Spartan 3E, Virtex-4 and Virtex-5 FPGAs and the results are presented. The simulation results show that applying the proposed method on circuits with less combinational depth reduces the required number of test configurations on average by 35% when compared with the latest method available in the literature.

Design and Implementation of Fuzzy Controller on FPGA

Fuzzy Logic Controller (FLC) systems have emerged as one of the most promising areas for Industrial Applications. The highly growth of fuzzy logic applications led to the need of finding efficient way to hardware implementation. Field Programmable Gate Array (FPGA) is the most important tool for hardware implementation due to low consumption of energy, high speed of operation and large capacity of data storage. In this paper, instead of an introduction to fuzzy logic control methodology, we have demonstrated the implementation of a FLC through the use of the Very high speed integrated circuits Hardware Description Language (VHDL) code. FLC is designed for an armature control DC motor speed control. VHDL has been used to develop FLC on FPGA. A Sugeno type FLC structure has been used to obtain the controller output. The controller algorithm developed synthesized, simulated and implemented on FPGA Spartan 3E xc3s500e-4fg320 board.

Finite-State Machine Motion Controller: Servo Drives

Digital controllers are used for modern power converter control and industrial automation. The functionality of the finite-state machine (FSM) provides an ideal platform for building a high-frequency field-programmable gate array (FPGA) controller for power electronics applications. This article develops the design of a current-control loop and the selection of switching logic for three-phase switching converters and ac electrical machines. The main design specifications are robustness to load and electrical parameters, fast dynamic response, reduced switching frequency, and simple hardware implementation. A discrete-event-type controller is proposed to meet previous specifications, designed as finite state automaton and implemented with an FPGA device. Furthermore, the actual controller architecture is based on the FPGA Spartan 3E. The experimental results are presented using a brushless ac (BLAC) motor as the converter load. However, this does not limit the wider applicability of the proposed controller, as it is suitable for different types of ac loads (rectifiers, inverters).

Four Stage Pipelined 16 bit RISC on Xilinx Spartan 3AN FPGA

This paper describes the design and implementation of a 16 bit 4 stage pipelined Reduced Instruction Set Computer (RISC) processor on a Xilinx Spartan 3AN Field programmable gate array (FPGA). The processor implements the Harvard memory architecture, so the instruction and data memory spaces are both physically and logically separate. The RISC processor architecture presented in this paper is designed by six units, they are instruction cache, instruction unit, decode unit, execute unit, data cache unit and register file unit. The processor has been described using Verilog HDL, simulated using ModelSim 6.5-SE simulator and synthesized using Xilinx ISE 11.1i.The proposed processor has been implemented and physically tested Xilinx FPGA Spartan 3AN development board, It uses ChipScope Pro 9.2i embedded logic analyzer to monitor any or all of the signals in the design.

Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Advantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two synchronous designs to increase the resolution of the DPWM implemented on field programmable gate arrays (FPGA). The proposed circuits are based on the on-chip digital clock manager block present in the low-cost Spartan-3 FPGA series and on the I/O delay element (IODELAYE1) available in the high-end Virtex-6 FPGA series. These solutions have been implemented, tested, and compared to verify the performance of these architectures.

Codebook hardware implementation on FPGA for background subtraction

Object detection and tracking are main tasks in video surveillance systems. Extracting the background is an intensive task with high computational cost. This work proposes a hardware computing engine to perform background subtraction on low-cost field programmable gate arrays (FPGAs), focused on resource-limited environments. Our approach is based on the codebook algorithm and offers very low accuracy degradation. We have analyzed resource consumption and performance trade-offs in Spartan-3 FPGAs by Xilinx. In addition, an accuracy evaluation with standard benchmark sequences has been performed, obtaining better results than previous hardware approaches. The implementation is able to segment objects in sequences with resolution $$768\times 576$$ at 50 fps using a robust and accurate approach, and an estimated power consumption of 5.13 W.

Voltage Control Scheme for a Single-Phase Voltage Source Inverter Using Field Programmable Gate Array

The work focuses on the design and implementation of a field programmable gate array (FPGA) based voltage controller for a single-phase voltage source inverter (VSI) with an inductance-capacitance (L-C) filter. The control algorithm of the open loop and closed loop control schemes of the controller are designed using hardware descriptive languages (VHDL and VerilogHDL) and are implemented using Xilinx SPARTAN 3E FPGA. The sinusoidal pulse-width modulation (SPWM) technique is utilised to realise the controller with a provision to change the modulation index in response with varying load conditions. Suitable L-C filter is designed to minimise the undesirable frequency components in the output voltage. The efficacy of the proposed control schemes in FPGA is validated via successful interface with a prototype VSI and the experimental verification of the controllers are carried out under different loading conditions.

Computerised Speech Processing in Hearing Aids using FPGA Architecture

The development of computerized speech processing system is to mimic the natural functionality of human hearing, because of advent of technology that used Very Large Scale Integration (VLSI) devices such as Field Programmable Gate Array (FPGA) to meet the challenging requirement of providing 100% functionality of the damaged human hearing parts. Here a computerized laboratory speech processor based on Xilinx Spartan3 FPGA system was developed for hearing aids research and also presented comparison details of the commercially available Hearing Aids. The hardware design and software implementation of the speech processor are described in detail. The FPGA based speech processor is capable of providing high- rate stimulation with 12 electrodes against conventional 8 electrodes in earlier research. Using short biphasic pulses presented either simultaneously or in an interleaved fashion. Different speech processing algorithms including the Continuous Interleaved Sampling (CIS) strategy were implemented in this processor and tested successfully.

Theory of Flying-Adder Frequency Synthesizers—Part I: Modeling, Signals' Periods and Output Average Frequency

This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts: Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edges in the FA's multiplexer's output establishes a discrete-time index that is used to analytically derive the fundamental discrete-time periods of all FA's signals. The continuous-time intervals between the rising edges are calculated and used to derive the fundamental continuous-time periods of the signals from the corresponding discrete-time ones. It is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified. The FA's output average frequency, along with its maximum and minimum values, is analytically derived by calculating the number of cycles in the output signal within a fundamental continuous-time period of it. The relationship between the average and the fundamental output frequencies is also established, indicating the potential frequencies and density of output spurious frequency components. Part II of the paper characterizes the timing structure of the output signal, providing analytical expressions of the pulses' locations, analytical strict bounds of the timing irregularities, and exact analytical expressions of several standard jitter metrics. Spectral properties of the output waveform are presented, including the dominance of the frequency component at the average frequency, and analytical expressions of the dc value and average power of the output signal are derived. The FA has been implemented in a Xilinx Spartan-3E field-programmable gate array, and spectral measurements are presented, confirming the theoretical results. Extensive MATLAB simulation has also been used to generate numerous examples illustrating the developed theory.

Theory of Flying-Adder Frequency Synthesizers—Part II: Time- and Frequency-Domain Properties of the Output Signal

This is a rigorous mathematical theory of the operation of the flying-adder (FA) frequency synthesizer (also called direct digital period synthesizer). The paper consists of two parts. Part I presents a detailed mathematical model of the FA synthesizer, capturing the relationships between the properties of the FA's output and internal signals and the FA's parameters. The counting of the rising edges in the FA's multiplexer's output establishes a discrete-time index that is used to analytically derive the fundamental discrete-time periods of all the FA's signals. The continuous-time intervals between the rising edges are calculated and used to derive the fundamental continuous-time periods of the signals from the corresponding discrete-time ones. It is shown that the FA behaves differently within different ranges of the frequency word, and the practically useful range is identified. The FA's output average frequency, along with its maximum and minimum values, is analytically derived by calculating the number of cycles in the output signal within a fundamental continuous-time period of it. The relationship between the average and the fundamental output frequencies is also established, indicating the potential frequencies and density of output spurious frequency components. Part II of the paper characterizes the timing structure of the output signal, providing analytical expressions of the pulses' locations, analytical strict bounds of the timing irregularities, and exact analytical expressions of several standard jitter metrics. Spectral properties of the output waveform are presented, including the dominance of the frequency component at the average frequency, and analytical expressions of the dc value and average power of the output signal are derived. The FA has been implemented in a Xilinx Spartan-3E field-programmable gate array, and spectral measurements are presented, confirming the theoretical results. Extensive MATLAB simulation has also been used to generate numerous examples, illustrating the developed theory.

High-Speed, SAD Based Wavefront Sensor Architecture Implementation on FPGA

Wavefront aberrations caused by turbulent or rapidly changing media can considerably degrade the performance of an imaging system. To dynamically compensate these wavefront distortions adaptive optics is applied. We developed an affordable adaptive optic system which combines CMOS sensor and Liquid Crystal on Silicon (LCOS) display technology with the Field Programmable Gate Arrays (FPGA) devices parallel computing capabilities. A high-speed, accurate wavefront sensor is an elemental part of an adaptive optic system. In the paper, an efficient FPGA implementation of the Sum of Absolute Differences (SAD) algorithm, which accomplishes the correlation-based wavefront sensing, is introduced. This architecture was implemented on a Spartan-3 FPGA which is capable of real-time (>500 fps) measuring the incoming wavefront.

A Novel Digital Implementation of AC Voltage Controller for Speed Control of Induction Motor

In this paper, a novel, simple and reliable digital firing scheme has been implemented for speed control of three-phase induction motor using ac voltage controller. The system consists of three-phase supply connected to the three-phase induction motor via three triacs and its control circuit. The ac voltage controller has three modes of operation depending on the shape of supply current. The performance of the induction motor differs in each mode where the speed is directly proportional with firing angle in two modes and inversely in the third one. So, the control system has to detect the current mode of operation to choose the correct order for the firing angle of triacs. Three sensors are used to feed the line currents to control system to detect the mode of operation. The control strategy is implemented using a low cost Xilinx Spartan-3E field programmable gate array (FPGA) device. Three PI controllers are designed on the FPGA to control the system for the three modes. Simulation of the system is carried out using PSIM computer programme. The simulation results show stable operation for different loading conditions especially in mode 2/3. The simulation results have been compared with the experimental results from laboratory prototype.

A novel digital implementation of AC voltage controller for speed control of induction motor

In this paper, a novel, simple and reliable digital firing scheme has been implemented for speed control of three-phase induction motor using ac voltage controller. The system consists of three-phase supply connected to the three-phase induction motor via three triacs and its control circuit. The ac voltage controller has three modes of operation depending on the shape of supply current. The performance of the induction motor differs in each mode where the speed is directly proportional with firing angle in two modes and inversely in the third one. So, the control system has to detect the current mode of operation to choose the correct order for the firing angle of triacs. Three sensors are used to feed the line currents to control system to detect the mode of operation. The control strategy is implemented using a low cost Xilinx Spartan-3E field programmable gate array (FPGA) device. Three PI controllers are designed on the FPGA to control the system for the three modes. Simulation of the system is carri...

Series–parallel pipeline architecture for high-resolution catadioptric panoramic unwrapping

To implement high-speed panoramic unwrapping of high-resolution catadioptric omnidirectional images on field-programmable gate array (FPGA), a novel design technique of pipeline architecture is proposed, named a ‘series–parallel pipeline’. Based on the strategy of ‘block prefetching’, catadioptric omnidirectional images are divided into image blocks before loading into the pipeline. Multiple functional sub-modules are copied to carry out the relatively time-consuming steps in parallel whereas fewer sub-modules or only one sub-module is created to carry out those less time-consuming steps. The number of copies is determined by the proportion of execution time of each step, and several neighbouring basic units are combined to form a ‘unit package’ before loading into the pipeline. The basic units in one ‘unit package’ are processed in series while carrying out the less time-consuming steps, but processed in parallel while carrying out the more time-consuming steps. A hardware pipeline design of series–parallel architecture is implemented on Xilinx Spartan-3 FPGA, which is able to unwrap one catadioptric omnidirectional image with size 1024×1024 into one cylindrical panorama with size 3200×768 at 12.480 ms per frame when the system clock is 100 MHz.