Series–parallel pipeline architecture for high-resolution catadioptric panoramic unwrapping

Abstract

To implement high-speed panoramic unwrapping of high-resolution catadioptric omnidirectional images on field-programmable gate array (FPGA), a novel design technique of pipeline architecture is proposed, named a ‘series–parallel pipeline’. Based on the strategy of ‘block prefetching’, catadioptric omnidirectional images are divided into image blocks before loading into the pipeline. Multiple functional sub-modules are copied to carry out the relatively time-consuming steps in parallel whereas fewer sub-modules or only one sub-module is created to carry out those less time-consuming steps. The number of copies is determined by the proportion of execution time of each step, and several neighbouring basic units are combined to form a ‘unit package’ before loading into the pipeline. The basic units in one ‘unit package’ are processed in series while carrying out the less time-consuming steps, but processed in parallel while carrying out the more time-consuming steps. A hardware pipeline design of series–parallel architecture is implemented on Xilinx Spartan-3 FPGA, which is able to unwrap one catadioptric omnidirectional image with size 1024×1024 into one cylindrical panorama with size 3200×768 at 12.480 ms per frame when the system clock is 100 MHz.