Spartan-6 Field Programmable Gate Array Research Articles

A high-resolution and glitch-free all-digital variable length ring oscillator design on an FPGA

This paper proposes an all-digital variable length ring oscillator (VLRO) circuit that is capable of easily controlling its output frequency without generating glitches at the frequency transitions on a field programmable gate array (FPGA). It includes two main blocks: 1) A coarse-tuning block is to widen the frequency range and 2) A fine-tuning block which is based on a dedicated high-speed carry chain is devised to improve the frequency resolution. Thanks to the use of high-speed carry chain, our circuit achieves a fine-grained delay resolution of 50 ps in average, which has a finer resolution than that of the state-of-the-art VLRO design in which the glitch problem has been solved with “lookup table” based coarse-grained delay lines. The proposed VLRO has been implemented on a Xilinx Spartan-6 FPGA for verifying its functional/timing correctness. It switches correctly between 22 different coarse-grained frequencies and 21 different fine-grained frequencies under different supply voltages.

Energy Efficient and Side-Channel Secure Cryptographic Hardware for IoT-Edge Nodes

Design of ultralightweight but secure encryption engine is a key challenge for Internet-of-Things edge devices. This paper explores the system level design space for an ultralow power image sensor node for secure communication and proposes an optimized datapath architecture for 128-bit SIMON (SIMON128), a lightweight block cipher, for minimal performance, power, and area overheads with increased level of side-channel security. Various datapath architectures for SIMON are explored for simultaneously increasing energy-efficiency and resistance to power-based side-channel analysis (PSCA) attacks. Alternative datapath architectures are implemented on ASIC (15 nm CMOS) and field programmable gate array (FPGA) (Spartan-6, 45 nm) to perform power, performance, and area analysis. We show that, although a bitserial datapath minimizes area and power, a round unrolled datapath provides $80{\times }$ higher energy-efficiency and $143{\times }$ higher performance, compared to the baseline bitserial design. Moreover, the PSCA measurements performed using Sakura-G board with Spartan-6 FPGA, demonstrate that a 6-round unrolled datapath improves minimum-traces-to-disclosure for correlation power analysis (CPA) by at least $384{\times }$ over baseline bitserial design with no successful CPA even with 500 000 measurements. Finally, application to the image-sensor node demonstrates that optimized unrolled SIMON128 can provide equivalent performance to AES128 at lower area, higher energy efficiency, and improved side channel security.

An efficient AES implementation using FPGA with enhanced security features

Data transferred in an electronic way is vulnerable to attacks. With an aim to protect data for secure communication, a new Hybrid non pipelined Advanced Encryption Standard (AES) algorithm based on traditional AES algorithm with enhanced security features is proposed in this work. Abysmal analysis of the AES algorithm implies that the security of AES lies in the S-box operations. This paper presents a new approach for generating S-box values (modified S-box) and initial key required for encryption/encryption (improved key generation) using PN Sequence Generator. The AES algorithm with proposed modifications shows significant improvement in the encryption quality as compared to traditional AES algorithm. The traditional AES algorithm equipped with proposed novel modified S-box technique and improved key generation technique gives an avalanche effect of 60% making it invulnerable to attacks. The proposed design is synthesized on various Field Programmable Gate Array (FPGA) devices and compared to the existing designs resulting in significant improvement in throughput. The proposed design is implemented on Spartan6 FPGA device.

A Real-Time QRS Detection System With PR/RT Interval and ST Segment Measurements for Wearable ECG Sensors Using Parallel Delta Modulators.

This paper presents a real-time electrocardiogram (ECG) monitoring system for wearable devices. The system is based on the proposed parallel delta modulator architecture with local maximum point and local minimum point algorithms to detect QRS and PT waves. Therefore, using the proposed system and algorithm, real-time PR and RT intervals, and ST segment measurements can be achieved in long-term wearable ECG recording. The algorithm is tested with the MIT-BIH Arrhythmia Database for QRS complex detection and with the QT Database for the P and T wave detections. The simulation result shows that the algorithm achieves above 99%, 91%, and 98% accuracy in the QRS complex, P wave, and T wave detections, respectively. Experimental results are presented from the system prototype, in which the parallel delta modulator circuits are fabricated in IBM 0.13$\mu \text{m}$ standard CMOS technology and the algorithms are implemented in a Xilinx Spartan-6 field programmable gate array (FPGA). The parallel delta modulators consume 720nW at 1kHz sampling rate with $\pm$0.6V power supply. The proposed system has the potential to be applied in future long-term wearable ECG recording devices.

Smart grid security with AES hardware chip

Smart grid is the upgradation of the existing grid in terms of cost, communication infrastructure, internet of things and reliable technologies. In ambitious flagship programme of digital India-project an initiative of India, the potential fields of the missions are identified in the area are smart energy, smart grids, smart homes and smart cities. More than 100 smart cities are planned for information and communication technology driven solutions with big data analytics in India. The exponential growth in smart grids has given certain security risks, cyber threats and protection of stored data as Nation security. Smart Grids, comprising of several communication, monitoring intelligent, metering and electrical equipment used in power grid, have a greater exposure to grid security and cyber-attacks which are potentially disrupt distribution in a city. The paper discusses the electrical grid, challenges in smart grid and the use of Advanced Encryption Standard (AES) algorithm enable with field-programmable gate array (FPGA) hardware in smart grids. The AES encryption and decryption chip is designed in Xilinx ISE 14.2 software, synthesized on SPARTAN-3E FPGA and verified with some test cases to ensure that AES can be employed in smart grid security and communication infrastructure.

Generic high resolution PET detector block using 12 × 12 SiPM array

With the advancement of the Silicon Photomultiplier (SiPM) technology, these devices are becoming the mainstream for use in high resolution PET detectors especially where the compatibility with magnetic field is critical. Large-area SiPM arrays are now widely used in high resolution PET detector modules. The challenges are emerged in the readout and timing circuitry by the increase of pixel density in the area. The application-specific integrated circuits (ASICs) are developed to readout arrays with standard anode/cathode outputs. SiPM detection principle, which produces dark current noise in the inactive pixels, makes the multiplexing techniques more challenging rather than the PMT signals. In this work a new generic PET detector block using SiPM arrays with three outputs (anode, cathode, and fast) is presented which is suitable for applications in small animal, brain, and clinical PET imaging. The block detector accepts a 12 × 12 array with both standard and fast output signals with an overall detector dimension of 50 × 50 mm2. A new version of the scrambled crosswire readout (SCR) method was implemented to reduce 144 ‘fast outputs’ to 9 tile signals and 144 standard outputs to 16 energy channels. The tile signals are also used to generate time pickoff information for timing resolution. We implemented time-to-digital converter (TDC) in Xilinx’s SPARTAN6 field programmable gate array (FPGA) by using the 64-tap delay line. This low cost chip performs all required processes for position, energy, time, and interface architecture. The attached 24 × 24 LYSO:Ce array with 2 × 2 × 10 mm3 pixels is imaged and pixels are resolved clearly in the room temperature. The measured energy resolution of the detector block after calibration for all crystal pixels is 12.4% at 511 keV. Also, the coincidence resolving time for two identical modules was measured at 1.85 ns.

Facial Expression Emotion Detection for Real-Time Embedded Systems

Recently, real-time facial expression recognition has attracted more and more research. In this study, an automatic facial expression real-time system was built and tested. Firstly, the system and model were designed and tested on a MATLAB environment followed by a MATLAB Simulink environment that is capable of recognizing continuous facial expressions in real-time with a rate of 1 frame per second and that is implemented on a desktop PC. They have been evaluated in a public dataset, and the experimental results were promising. The dataset and labels used in this study were made from videos, which were recorded twice from five participants while watching a video. Secondly, in order to implement in real-time at a faster frame rate, the facial expression recognition system was built on the field-programmable gate array (FPGA). The camera sensor used in this work was a Digilent VmodCAM — stereo camera module. The model was built on the Atlys™ Spartan-6 FPGA development board. It can continuously perform emotional state recognition in real-time at a frame rate of 30. A graphical user interface was designed to display the participant’s video in real-time and two-dimensional predict labels of the emotion at the same time.

DSPWM multilevel technique of 27-levels based on FPGA for the cascaded DC/AC power converter operation

Summary In this paper, a digital sinusoidal pulse width modulation (DSPWM) multilevel technique of 27-levels based on field programmable gate array (FPGA) is introduced, as an alternative to control of the direct current/alternating current multilevel power converters. The implementation of this technique with an FPGA XC3S500E model is achieved in the Xilinx Spartan-3E FPGA platforms. An experimental prototype is implemented by 3-cascaded H-bridges controlled by the DSPWM multilevel technique, generating high efficiency, low cost, and lower harmonic content. The efficiency of the DSPWM multilevel technique using R, RL, RC, and RLC loads connected to the power network is verified.

An FPGA-based nuclear pulse generator with a prescribed amplitude distribution

A design of a low-cost electrical pulse generator capable of producing random pulses with exponentially decaying tail as coming from a nuclear detector is described. The generator can generate periodic single or double pulses of a user-defined amplitude and decay time, or randomly occurring pulses with amplitudes drawn at random from a user-prescribed probability density function. The electronics is based on a low power consumption Spartan-6 field-programmable gate array (FPGA) and a 14-bit digital to analog converter (DAC) running at frequency of 40 MHz, and a complete technical documentation to build the generator is available online.

FPGA-Based Implementation of Dual Kalman Filter for PV MPPT Applications

The way of implementing an adaptive maximum power point tracking algorithm for photovoltaic (PV) applications in a field programmable gate array (FPGA) is described in this paper. A dual Kalman filter allows estimating the settling time of the whole system, including the PV source and the dc/dc converter controlling the operating point thereof, so that the tracking algorithm self adapts its parameters to the actual weather conditions. The real-time identification need of this application requires an FPGA platform, so that the intrinsic algorithm parallelism is exploited and the execution time is reduced. The tradeoff solutions proposed in this paper, accounting for the algorithm complexity and the limited FPGA hardware, as well as some solutions for optimizing the implementation are described. The proposed adaptive algorithm is implemented in a low-cost Xilinx Spartan-6 FPGA and it is validated through experimental tests.

FPGA-based Volleyball Player Tracker

The significant challenge facing sport science is how to grasp the flow of the game and analyze the situation of amatch. The use of information technology will facilitate to achieve the goal. The technical issues from the practical application perspective can be classified into three main points: computation speed, system size and complex data analysis considering the accuracy. In this paper, for accelerating image recognition and object tracking, we propose a one-dimensional data pipeline architecture on a field-programmable gate array (FPGA). It satisfies both of high-speed streaming computation and small-sized circuits by considering spatiotemporal data dependence. Volleyball games have been chosen as a target application. The proposed system will identify the position of six volleyball players within real time. The design on an FPGA includes pre-processing, color filtering, digitalization, noise reduction, template matching, and so on. The design was implemented and evaluated on Atlys Spartan-6 FPGA Trainer Board with one XILINX Spartan-6 LX45 FPGA. The computational performance achieves 100 frames per second at SVGA 800 by 600 pixel resolution. And our design has good scalability; the performance can easily be enhanced when the larger FPGA is used. The proposed system is also compact, which is composed of one Atlys board and one Atlys VmodCAM stereo-camera board. The average-accuracy rates of pregame situation and during a match are 87.1% and 65.7%, respectively. Since the input is streaming data, we can improve the accuracy by considering the previous and the next frames. They could be improved to 90.4% and 72.2%, respectively, when we adopt template matching with a moving average filter.

Web-based DAQ systems: connecting the user and electronics front-ends

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

FPGA Implementation and Analysis of the Block Cipher Mode Architectures for the PRESENT Light Weight Encryption Algorithm

Objective: This paper presents the Field Programmable Gate Array (FPGA) implementations of the different block cipher mode architectures of the ISO standardized light weight block cipher PRESENT, designed for resource constrained devices. Methods/ Statistical Analysis: The performance evaluations compare the implementations of the different block cipher modes, namely Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback Mode (CFB), Output Feed Back Mode (OFB) and CounTeR (CTR) mode for the PRESENT cipher. The throughput of encryption of three successive 64 bit blocks of data ranges from 565.312Mbps to 574.784Mbps for the modes other than the cipher feedback mode in the Spartan-3 FPGA. The throughput for providing confidentiality through encryption in the cipher feedback mode arrives as 68.912 Mbps, 155.392Mbps and 300.8 Mbps for a 64 bit block of data for the input streams of size 8 bits, 16 bits and 32 bits respectively. Findings: The throughput of the block cipher mode hardware architectures of the light weight cipher PRESENT demonstrates the high speed performance of the cipher in encryption/decryption of data as blocks and streams. Application/ Improvement: The significance of the proposed work is to know the hardware performance of the different modes of operation for the light weight block cipher PRESENT. The performance estimation of the block cipher modes operations of the PRESENT cipher definition in hardware have been carried out for the first time.

Design of Out-of-Order Floating-Point Unit

Objective: Field Programmable Gate Arrays (FPGAs) are often used to accelerate hardware systems by implementing algorithms on hardware. This paper presents the design and implementation of a fully pipelined single-precision Floating-Point Unit (FPU) on a Spartan-6 FPGA chip. Methods: This paper presents a high-speed, modular design for improving the performance of such applications. While the proposed design is capable of performing basic arithmetic operations and square-root extraction, its modularity enables designers to add more functionality easily; or remove modules that they deem unnecessary for a particular application. Findings: The investigation shows that the adder and multiplier modules can be clocked at over 300 MHz and the top-module at over 200 MHz High operating frequencies were achieved by pre-computing possible values in earlier pipelining stages, then correcting results in later pipelining stages. It was also found that splitting longer operations in the critical path is a better alternative than processing the whole operation at once. Limiting “Max_Fanout”, an attribute provided by Xilinx XST tool, proved valuable in reducing delays on overloaded nets. Applications: This FPU would be a worthwhile addition as a floating-point extension in fixed-point processors for applications such as spectrum analyzers, 3D graphics, and audio processing units.

HSTL IO Standards Based Processor Specific Green Counter Design on 90nm FPGAAbhay Saxena

Extending battery life and increase in portability of modern electronic devices and gadgets are the main motives behind the Green Computing which is also known by similar terms like energy efficient design or low power design or green design. Such efficiency is only possible if all the components of processor are also energy efficient. In this work, the researchers tried to analyze the energy optimization possibility in counter design by selection of energy efficient IO standards. The researchers had used High Speed Transceiver Logic for the purpose of energy efficient counter design on Spartan3 (90nm) FPGA (field-programmable gate array) using VHDL (VHSIC Hardware Description Language) hardware description language along with the Xilinx ISE simulator for the analysis and synthesis of counters. Spartan 3 with 90 nm low power is used to achieve substantial power savings. Here, researchers have used five different HSTL IO standards for this work. The standards used are HSTL_I, HSTL_III, HSTL_III_18, HSTL_III_DCI and HSTL_II_18. With these sets of IO standards, Researchers had run their counter design on various device operating frequencies (1.0 GHz to 4.0 GHz). The results clearly indicate that this dynamic frequency (1.0 GHz in lieu of 4.0 GHz) scaling had saved 45% of total power.

Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems.

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at 3.6×107 synaptic events per second per 16k-neuron node in the hierarchy.

Ring oscillators analysis for security purposes in Spartan-6 FPGAs

Nowadays, many digital applications domains are arising and posing new design issued and challenges related to the security and trustworthiness. Physically Unclonable Functions (PUFs) are emergent and promising solutions in providing some security mechanisms, such as key storing and generation, challenge/response provider, and protection of Intellectual Properties (IPs). As a huge range of embedded applications is deployed on Field Programmable Gate Arrays (FPGAs) devices, most widespread PUFs’ architectures are based on Ring Oscillators (ROs), as they are suitable for an implementation on programmable devices. ROPUF exploits comparisons of measured frequencies, obtained by picking a RO pair, aiming to generate bit responses. In this paper, we present a study of the frequencies characteristics, implementing ROs on a significant number of Xilinx Spartan 6 devices, in order to statistically characterize the oscillations, evaluating the impact of some external uncontrolled parameters that can disturb and alter their original qualities, useful to validate the effectiveness of the ROPUF.

Development of BLDC Motor-Based Elevator System Suitable for DC Microgrid

In recent days, utilization of the renewable energy sources has been emphasized in high-rise buildings, where dc microgrid is established. It is known that the brushless direct current (BLDC) motors have smooth speed control, high-power density, and less complexities in power converter and controller when operated with dc supply as compared to other electrical motors. Hence, this paper enunciates the scope of using BLDC motors for elevator systems suitable for operating with a dc microgrid. For analyzing the proposed BLDC motor-based elevator system, a MATLAB mechatronic simulation model has been developed by inserting various electrical and mechanical components. Four quadrant operation of the proposed elevator system has also been indicated with the simulation results. To demonstrate the successful working of the proposal, a prototype elevator system has been designed and developed in the laboratory. The overall closed-loop controller has been implemented using a Xilinx Spartan-3E field programmable gate array (FPGA). Experiments have been conducted for the upward and downward movement of the elevator cabin with and without load and the findings are given in this paper. Regenerative braking is also possible for the proposed system by employing a suitable gear mechanism in place of worm gear.

FPGA Implementation of ALU using Vedic Mathematics

Arithmetic and Logic Unit (ALU) is the most crucial and core component of central processing unit as well as of number of embedded systems and microprocessors. ALU consists of many computational units like adders, multipliers, logical units etc. Vedic Mathematics concepts are proposed here for designing the computational units of an 8-bit ALU. Here, a high-speed 8×8 bit multiplier is proposed which is based on the Vedic multiplier mechanism. A divider based on vedic mathematics is also proposed here. The proposed Vedic mathematics based ALU is designed using high level hardware description language – Verilog, followed by synthesization using EDA tool, Xilinx ISE 14.1. Finally, the synthesized circuit has been implemented on Xilinx Spartan-6 Field Programmable Gate Array (FPGA) device.

Implementation of FPGA-Based Charge Control for a Self-Sufficient Solar Tracking Power Supply System

This study used a field-programmable gate array (FPGA) with a Xilinx Spartan-3 FPGA to implement Reflex charge control in a dual-axis solar tracking system with maximum power point tracking (MPPT). The chaos embedded particle swarm optimization method was used to search for the optimum gain constants of the PI controller and the Reflex charging frequency. This scheme not only increases the output power of solar panels but also has a significant effect on switching loss and oscillation of solar charging. The experiment results showed that the proposed method can also significantly improve temperature rise, and that charging efficiency is also better than it is in a traditional charge mode. The results also showed that charging power was enough for solar tracking and the requirements of the charging system. The most significant contribution of this paper is that the scheme can be applied to any active solar tracking and charging system.