Spartan-6 Field Programmable Gate Array Research Articles

Build-in compact and efficient temperature sensor array on field programmable gate array

Digital sensor arrays based on ring oscillators are used to monitor the temperature of Field Programmable Gate Array (FPGA) chips, but traditional sensor structures using binary frequency counters consume excessive hardware logic resources. This paper proposed a compact temperature sensor array that used low-decoding-complexity linear feedback shift registers (LFSR) as a frequency counter to efficiently count the ring oscillator frequency. We implemented an experimental system on a Spartan-6 FPGA, and the logic resource consumption of the entire system was 927 Look-Up-Tables (LUTs) with an overhead of only 10%. The single sampling time was approximately 40 μs. The proposed temperature sensor array has good temperature sensing capabilities, and the measured error is ±0.9°C(3σ).

Efficient Hardware Implementation for Quantum key Distribution Protocol using FPGA

This paper presents a new hardware implementation of the quantum key distributed cryptography protocol using Field Programmable Gate Array (FPGA). In many security applications, the software implementations of key distribution algorithms are slow and inefficient. In order to solve this problems, new hardware architecture was proposed to speed up the performance and flexibility of key distribution algorithms. The concurrent computing designs quantum key distribution protocol with reducing the hardware area, producing a high throughput and low latency. It also showed high speed processing and consumed low power. An efficient hardware architectural model for quantum key distribution protocol was developed using very high-speed integrated circuit hardware description language (VHDL). This hardware designed to be used with any quantum key distribution protocol to distribution the secret key securely. The hardware implemented and test with Spartan-3 FPGA board and the results show a throughput of 8 Mbps and efficiency of 1.6 Mbps/slice.

RETRACTED: Human tracking of track and field athletes based on FPGA and computer vision

An essential issue that sports science faces in understanding the game's flow is to analyze the game's situation. The use of information technology can help to achieve this goal. Computing speed, the size of the system, consider the accuracy of the complex data analysis. From the practical application of views, technical problems can be divided into three significant respects. This article aims to accelerate image recognition and object tracking; propose a one-dimensional data pipeline architecture on a Field-Programmable Gate Array (FPGA). It is met by a small circuit considering calculation and the spatiotemporal data dependency between two high-velocity flows. The volleyball game has been selected as the target application. FPGA design, pre-processing, color filtering, digitization, noise reduction, including such as template matching. Design and implementation by training stations of the Spartan-6 FPGA Xilinx Atlys of the Spartan-6 FPGA LX45 'were evaluated. Computing power will reach per 100 frames at a resolution of SVGA 800 × 600 pixels. Design, excellent with the scalability, can more easily improve the performance in the case of using a large FPGA. The proposed system consists of the Atlys substrate and Atlys VmodCAM stereo camera board. The average accuracy rate before the game situation and the game with 87.1 percent and 65.7 percent. Since the streaming input data, you can improve the precision by taking into account the previous and the next frame. And 90.4 percent will be able to improve to 72.2 percent by using a moving average filter and template matching.

An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

Blind source separation (BSS) is a problem that appears in many research fields. Fast Independent components analysis (FastICA) is one of the techniques to solve the problem. The researchers have verified the effectiveness of the technique through the offline analysis of the public datasets. The development of a real-time portable system involving such a computationally complex analysis requires an efficient hardware implementation of FastICA. A Field programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) are two promising hardware platforms to implement FastICA. This work proposes a new method, called ALgebraic Jacobi Method (ALJM), for performing eigenvalue decomposition (EVD) required for the implementation of FastICA. We use a simplification, a polynomial approximation, and the Newton-Raphson method for calculating the Jacobi rotation. In this way, we ensure hardware reusability between the EVD stage and the weight vector estimation (WVE) stage of FastICA which reduces the computational complexity and the power consumption, without compromising its computation speed. We evaluate the ALJM-based FastICA by performing BSS on the linear mixtures of the deterministic and the random signals and comparing the performance results with the existing methods. After verifying its functionality and numerical stability, we propose a scalable systolic processing array (SPA) for the ALJM-based FastICA and implement it on Spartan-6 FPGA. By comparing the existing implementations of FastICA, in terms of speed, area, and power, we conclude that the ALJM-based FastICA is one of the most efficient methods for prototyping and commercializing a real-time portable system comprising FastICA.

A Customized Floating-point Processor Design for FPGA and ASIC based Thermal Compensation in High-precision Sensing

There are many types of sensors which require large dynamic range as well as high accuracy at the same time. Barometric altimeter is an example of such sensors. The signal processing techniques in the sensors are normally implemented using Field Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs). The sensing variable in such type of the sensors is unwantedly environment dependent. So, for ensuring accuracy of the sensors this environmental dependency is minimized using the modeling and compensation techniques. In this work we have proposed a digital architecture for a programmable high precision computational unit which can be implemented in the FPGA or ASIC running the sensing algorithm of the sensors. This architecture can be used to implement polynomial compensation and it also supports reading and writing of the corresponding calibration coefficients even after the development of the sensors. Moreover, the architecture is platform independent. The architecture have been simulated for different FPGAs and ASIC and it has fulfilled the speed, accuracy and programmability requirements of the type of the sensors. The architecture has also been implemented and verified in a prototype of the barometric pressure sensor on Spartan-6 FPGA.

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.

On-Chip Trust Evaluation Utilizing TDC-Based Parameter-Adjustable Security Primitive

Field-programmable gate arrays (FPGAs) are integrated circuits (ICs) that can be reconfigured to the desired functionalities, without manufacturing dedicated chips. Due to their programmable nature, FPGAs have been prevalent in the large majority of modern systems. This raises high demands for verifying the security of circuit implementations on FPGAs, since they are vulnerable to hardware trojans (HTs) that can be inserted through modified configuration files. In this article, we propose an on-chip security framework to ensure the trustworthiness of circuit implementations on FPGAs at runtime. The core of the framework is a time-to-digital converter (TDC)-based hardware security primitive that can be predeployed on FPGAs to verify whether the FPGA-based designs are tampered with or corrupted by HTs. The parameter-adjustable TDC sensor, which is the primary component of the primitive, is carefully designed, adjusted, and implemented, thus the TDC sensor can monitor the transient voltage fluctuations within FPGAs with a high resolution. Versus statistical data analysis, tiny abnormal variations introduced by the Trojan insertion and activation are distinguished. Experimental results on Xilinx Spartan-6 FPGAs demonstrate the effectiveness of the proposed TDC-based on-chip trust evaluation framework and HT detection method.

A Smart Chair Sitting Posture Recognition System Using Flex Sensors and FPGA Implemented Artificial Neural Network

Sitting is the most common status of modern human beings. Some sitting postures may bring health issues. To prevent the harm from bad sitting postures, a local sitting posture recognition system is desired with low power consumption and low computing overhead. The system should also provide good user experience with accuracy and privacy. This paper reports a novel posture recognition system on an office chair that can categorize seven different health-related sitting postures. The system uses six flex sensors, an Analog to Digital Converter (ADC) board and a Machine Learning algorithm of a two-layer Artificial Neural Network (ANN) implemented on a Spartan-6 Field Programmable Gate Array (FPGA). The system achieves 97.78% accuracy with a floating-point evaluation and 97.43% accuracy with the 9-bit fixed-point implementation. The ADC control logic and the ANN are constructed with a maximum propagation delay of 8.714 ns. The dynamic power consumption is 7.35 mW when the sampling rate is 5 Sample/second with the clock frequency of 5 MHz.

Efficient and Lightweight FPGA-based Hybrid PUFs with Improved Performance

In recent years, Physically Unclonable Functions (PUFs) have emerged as a promising technique for hardware based security primitives because of its inherent uniqueness and low cost. In this paper, we present an area efficient hybrid PUF design on field-programmable gate array (FPGA). Our approach combines units of conventional RS Latch-based PUF (RS-LPUF) and Arbiter-based PUF (A-PUF) which is then augmented by the programmable delay lines (PDLs) and Temporal Majority Voting (TMV) for performance enhancement. The area of the hybrid PUF is relatively high when compared to few conventional PUF designs, but is significantly small when compared to other composite and hybrid PUF designs reported so far. The measured results on the Xilinx Spartan-6 FPGA demonstrate PUF signatures exhibits good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing.

A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

FPGA-Based High-Definition SPWM Generation With Harmonic Mitigation Property for Voltage Source Inverter Applications

High-resolution sinusoidal pulsewidth modulation (SPWM) switching is beneficial in order to achieve compact size and fine sinusoidal output of dc-ac converters. In this article, a novel field-programmable gate array (FPGA) based high-definition SPWM (HD-SPWM) architecture is proposed for adopting a scheme of integrating a lower frequency PWM train to a high-frequency SPWM train in order to suppress inverter output harmonics while achieving high resolution output. An optimized FPGA-based two-stage finite-state-machine (FSM) architecture is designed, where the initial stage decides pulsewidths of a lower frequency PWM train based on the premeditated pulsewidth of the high-frequency SPWM train, whereas in the final stage, lower frequency PWM pulsewidths are integrated with the high-frequency SPWM pulsewidths to generate updated pulsewidths of high-frequency SPWM, i.e., HD-SPWM. Moreover, a preformulation mathematical model is established for the calculation of duty-cycle count values of pulse trains to support the online adjustment of modulation index (MI) of the HD-SPWM. The proposed generation has the benefits of harmonic mitigation, online fine adjustment of MI, low-processing time, and requirement of a minor segment of a medium-sized FPGA; thereby, providing a good tradeoff between larger designs and higher performance. Theoretical calculations, characteristics, and design contemplations are specified, and the HD-SPWM generation is demonstrated through experimentation with a Xilinx Spartan-3 FPGA board.

A Dynamical Machine Control System using Simple Processing Unit Based-on FPGA

This paper aims to design a dynamic machine control system device. The proposed dynamic device models are a combination architecture of memory and Arithmetic-Logic Unit (ALU). The configuration of the memory has used a random access memory (RAM), and the configuration of ALU is the core of the central processing unit (CPU), which consists of two functions, namely the arithmetic unit and the logical unit. In this paper, the arithmetic unit consists of addition, subtraction, multiplication, and division, whereas the logical units are AND, OR, NOT, and XOR. The shifter circuit in this paper was also applied to complete the programming code instructions in a software approach. The arithmetic unit and logic unit selector path in the ALU configuration employed a multiplexer circuit. This paper used a top-down design technique by determining the components in implementation. By knowing the function and work of these components, it is much easier to combine the components employing the configuration code of the hardware description language, namely a Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The implementation of the VHDL code was configured into the Xilinx Spartan-3E Field Programmable Gate Array (FPGA) to determine the component consumption and the resulted delay time. The results obtained from the configuration of the ALU components consume 26 slices, 50 4-input look-up table (LUT), 17 input/output (I/O), and 17 Bonded IO, while the component delay time is 11,413 ns.

Digital Processing for Accurate Frequency Extraction in IFM Receivers

Extracting the unknown frequency of a radar pulse has been one of the most challenging aspects of instantaneous frequency measurement (IFM) receivers. The conventional IFM receivers are limited in accurate frequency extraction by their design. In this article, a digital processing unit is added to the conventional IFM to extract the frequency with higher accuracy. A 2–4 GHz IFM has been designed combining the compact conventional RF section with the new digital processing unit using a novel efficient frequency extraction algorithm. The algorithm of minimum mean square error (MMSE) estimator is explored for use within the IFM, and it is proven that it can achieve much higher frequency accuracy. The novelty of this article includes both investigation and development of the algorithm to be a good fit for the frequency extraction in IFM receivers and also a digital implementation of the algorithm which meets the minimum requirements of an industrial IFM. The design has been implemented using microstrip filters on Rogers substrate and a Spartan-3E field-programmable gate array (FPGA) processor. The measurement results show promising achievements and verify the principle idea of digital processing for accurate frequency extraction in IFM receivers. The designed and fabricated receiver reaches 1.7 MHz rms frequency error in the frequency band of 2–4 GHz, which is at least $10\times $ improvement with respect to the state-of-the-art works.

Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling

Field-programmable gate arrays (FPGAs) have been extensively used because of their lower nonrecurring engineering and design costs, instant availability and reduced visibility of failure, high performance, and power benefits. Reports indicate that previously used or recycled FPGAs are infiltrating the electronics’ supply chain and making the security and reliability of the critical systems and networks vulnerable. Current recycled integrated circuit (IC) detection procedures include parametric, functional, and burn-in tests that require golden or reference data. Besides, they are time consuming, require expensive equipment, and do not focus on FPGAs. In this article, we propose two recycled FPGA detection methods based on supervised and unsupervised machine learning algorithms. We develop a sophisticated ring oscillator (RO) design to exploit the degradation of lookup tables (LUTs) and use them in the proposed methods. In the supervised method, a one-class classifier is trained with RO frequencies, kurtosis, and skewness data obtained from unused FPGAs, which differentiates unused and aged FPGAs. The unsupervised method uses $k$ -means clustering and Silhouette value analysis to detect suspect recycled components with very little (if any) golden information. In addition, we introduce a voltage scaling-assisted RO frequency measurement technique that improves the classification. The proposed methods are examined for Spartan-3A and Spartan-6 FPGAs, and the result shows that both methods are effective in detecting recycled FPGAs, which experience accelerated aging for at least 12 h equivalent to 70 days in real-time age.

A Domain-Specific Processor Microarchitecture for Energy-Efficient, Dynamic IoT Communication

In this paper, we present a domain-specific processor architecture, named pulsed-index communication interface architecture (PICIA), for single-channel IoT communication based on the recently introduced pulsed-signaling protocols, according to which information is encoded as series of pulses representing ON bits. In addition to the traditional aspects of instruction set architecture (ISA) design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes domain-specific instructions that facilitate bit stream encoding and decoding based on the pulsed-signaling techniques. The domain-specific PICIA microarchitecture employs a set of optimized processing blocks that can be used programmatically to encode and decode the transmitted data in the most economical way. The PICIA allows customizations that support both standard pulsed-signaling techniques and specialized protocols that belong to the same family. The PICIA design further allows an amalgamation of software and hardware that significantly reduces the number of instructions required to implement a given communication interface without impacting the data rates and reliability of the pulsed-signaling protocols. The PICIA processor has been implemented in Verilog HDL and tested using a Xilinx Spartan-6 field-programmable gate array (FPGA). Furthermore, a 65-nm application-specific integrated circuits (ASIC) synthesis of the design confirms the small-footprint and low-power features of PICIA. The consumed power has been evaluated at $31.14~\mu \text{W}$ with an energy efficiency of less than 10 pJ/bit .

In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA

In this paper, a timing error predictor (TEP) for adaptive frequency scaling (AFS) is proposed on a field-programmable gate array (FPGA). The use of TEP-based AFS can minimize large timing margin which is added to a clock cycle time for tolerating process, voltage, and temperature (PVT) variations. On an FPGA, in general, the typical dynamic frequency scaling has used the feature of dynamic frequency synthesis (DFS) in a digital clock manager (DCM). However, it has a long locking time. Moreover, during the DCM reconfiguration for generating a new frequency, the lock signal of the DCM can be lost and it leads to possible glitches or spikes at the output. In this work, a variable-length ring oscillator (VLRO), which employs a high-speed carry chain in an FPGA, is proposed to replace the DCM for changing the frequency within one clock cycle without introducing any glitches. Furthermore, an in-situ TEP, which detects timing errors, is combined with VLRO to further reduce the timing margin of a target system. Our proposed in-situ TEP-based AFS scheme is applied to a [Formula: see text]-bit multiplier and implemented on a Spartan-6 FPGA device (XFC6SLX45). The functional correctness of the TEP is verified under various DC supply voltages and operating frequencies. The experimental results show that the proposed TEP-based AFS system switches the clock frequency correctly within two clock cycles and improves circuit performance up to [Formula: see text] the nominal operating condition by minimizing the timing margin.

Switched coupled inductor inverter-based interline dynamic voltage restorer with discrete wavelet transform-artificial neural network technique

An educational studies and understanding about theoretical and practical laboratory in power quality issues. Interline dynamic voltage restorer is used in the proposed system for mitigating voltage sag, swell, harmonics, and interruptions. The conventional topology of dynamic voltage restorer possessing voltage source inverter is modified into a switched coupled inductor inverter which has the clear edge in power transfer over the former one. The versatility of the controller is enhanced in this work by deploying an artificial neural network combined discrete wavelet transform. The artificial neural network and discrete wavelet transform aided pulse width modulation generation enhances the controller performance by mitigating the harmonics considerably. The simulation and experimental results reveal that interline dynamic voltage restorer renders solution for major power quality issues like voltage sag and swell. Interline dynamic voltage restorer-based SCII is implemented with field programmable gate array Spartan 6 controller and signal processing technique such as discrete wavelet transform that mitigates voltage sag and harmonics. Paper is constructed such that the students in Bachelor’s and Master’s program of Electrical engineering can understand the power quality, various issues, and mitigating the total harmonic distortion value. The equations related to real power transfer are derived which enable the students to clearly understand about the power exchange between the feeders. Further, it is applied in practical laboratory setup facility for understanding about power quality issues to students of both undergraduate and postgraduate courses.

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have been proposed for the Internet based on classical cryptography cannot be applied to IoT nodes as they are typically resource-constrained. A physical unclonable function (PUF) is a hardware-based security primitive and can be used to generate a key online or uniquely identify an integrated circuit (IC) by extracting its internal random differences using so-called challenge-response pairs (CRPs). It is regarded as a promising low-cost solution for IoT security. A logic reconfigurable PUF (RPUF) is highly efficient in terms of hardware cost. This article first presents a new classification for RPUFs, namely circuit-based RPUF (C-RPUF) and algorithm-based RPUF (A-RPUF); two Exclusive OR (XOR)-based RPUF circuits (an XOR-based reconfigurable bistable ring PUF (XRBR PUF) and an XOR-based reconfigurable ring oscillator PUF (XRRO PUF)) are proposed. Both the XRBR and XRRO PUFs are implemented on Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The implementation results are compared with previous PUF designs and show good uniqueness and reliability. Compared to conventional PUF designs, the most significant advantage of the proposed designs is that they are highly efficient in terms of hardware cost. Moreover, the XRRO PUF is the most efficient design when compared with previous RPUFs. Also, both the proposed XRRO and XRBR PUFs require only 12.5% of the hardware resources of previous bitstable ring PUFs and reconfigurable RO PUFs, respectively, to generate a 1-bit response. This confirms that the proposed XRBR and XRRO PUFs are very efficient designs with good uniqueness and reliability.