Inductive Source Degeneration Research Articles

A 40.3–50.5 GHz locking range transformer‐based injection‐locked frequency divider utilizing a high third harmonic rejection buffer

AbstractInjection‐locked dividers feature ultrahigh operating frequency, low power consumption, and low phase noise, making them suitable for Q‐band phase‐locked loop. This paper presents a transformer‐based divide‐by‐4 injection locking frequency divider with a high third harmonic rejection buffer based on 40‐nm CMOS technology. Employing a fourth‐order transformer resonator enhances the third‐order harmonic amplitude, increasing the injection efficiency and expanding the locking range. The proposed high third harmonic rejection buffer using a source degeneration inductor can effectively suppress the output of the third harmonic caused by the resonator, ultimately yielding a clean fundamental frequency signal. Simulation results demonstrate that the proposed divide‐by‐4 injection‐locked frequency divider (ILFD) achieves a locking range of 10.2 GHz (from 40.3 to 50.5 GHz) with 0 dBm input signal. The core divide‐by‐4 ILFD circuit consumes 4.6 mW power with a 0.9 V supply and occupies an area of 0.026 mm2.

A gyrator-C active inductor based tunable low noise amplifier for sub-GHz frequency range

The propose exhibits a tunable low noise amplifier (LNA), which provides the tunability at sub-GHz frequency range and hence can become choicest frequency range for 5 G applications. Common source (CS) with source degeneration inductor LNA is proposed; in which the inductor in source branch is replaced by gyrator-c active inductor which not only reduced the overall area of the circuit but can also be used to provide the feature of tunability by changing the bias voltage of CMOS based active resistor in feedback branch. Therefore, instead of having a LNA circuit for the fixed frequency, a single tunable LNA design can be used over a range of frequency from 1 GHz to 5 GHz. The proposed approach will provide the direct tuning to the circuit. The forward voltage gain achieved is greater than 10 dB, input matching parameter is less than −10 dB and the output matching parameter is less than −10 dB. The average power dissipated is 0.02 W. The results can be tuned by controlling the feedback voltage of tunable active inductor (Tunable_AI). The tunable results can be achieved up to the bandwidth of 1 GHz.

Robust Ku-Band GaN Low-Noise Amplifier MMIC

This paper employs the 0.2 μm ETRI GaN HEMT process on SiC to develop a Ku-band GaN low-noise amplifier monolithic microwave integrated circuit (MMIC) characterized by high-input power robustness for radar transceiver modules. A source degeneration inductor is employed to obtain the proposed amplifier’s stable operation and the compromised impedance trajectory of the maximum available gain and minimum noise figure. The analysis results show simultaneous gain and noise impedance matching, achieved using only a small number of passive elements. Furthermore, the proposed low-noise amplifier MMIC secures a linear gain of 21.3−22.6 dB, an input return loss of 19.6−21.4 dB, and a noise figure of 1.7−1.8 dB in the 15–16 GHz frequency range. It also exhibits an input 1 dB compression point of 0.4−1.5 dBm in the single-tone power test, and an input third-order intercept point of 5.8−10.1 dBm within the 15−16 GHz frequency range in the two-tone intermodulation distortion test.

A Folded Cascode CMOS Low Noise Amplifier with Transformer Feedback

This study proposes a folded cascode CMOS low noise amplifier (LNA) with transformer feedback, implemented using a 0.13-μm CMOS process for wireless local area network front-end module applications. Compared to a conventional cascode inductive source degeneration LNA (ISDLNA), the folded cascode ISDLNA significantly improved the input-referred third-order intercept point (IIP3) as well as the 1-dB compression point (P1dB) by ensuring a large voltage headroom. Furthermore, the designed LNA also achieved a low noise figure (NF), while also saving the silicon area by magnetically coupling the source and folding inductors. When tested experimentally, the proposed LNA showed an S21 of 11.0 dB and an NF of 2.6 dB, while achieving an <i>S</i><sub>11</sub> of -7 dB at the operating frequency of 2.4 GHz. The measured input P1dB and IIP3 were -5.6 dBm and +2.5 dBm, respectively. The power dissipation was 9.6 mW from a 1.2-V supply voltage.

A Low Noise Amplifier with 27 dB Gain and 1.78 dB Noise for Satellite Communications with 0.1 µm GaAs pHEMT Technology

This paper proposes a design of a 38 GHz Low Noise Amplifier (LNA) that uses a three-stage common source inductive degeneration topology with a gain of 27 dB and noise figure of 1.78 dB using 0.1 µm GaAs pHEMT as an active device. The novelty of the design is the usage of inductive load in series with the resistor instead of resistive load, resulting in higher gain performance. A recent pp1010 active device of WIN foundry was explored for this LNA design at the Q band. The high transition frequency offered by this technology succeeded in obtaining competitive results with a minimum number of cells. The designed LNA obtained the lowest noise compared to other recently published LNA designs at the Q band. The total power consumption of this design is 57 mW.

Multi-objective optimization of CMOS low noise amplifier through nature-inspired swarm intelligence

This paper presents the application of two swarm intelligence techniques, multi-objective artificial bee colony (MOABC) and multi-objective particle swarm optimization (MOPSO), to the optimal design of a complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) cascode with inductive source degeneration. The aim is to achieve a balanced trade-off between voltage gain and noise figure. The optimized LNA circuit operates at 2.4 GHz with a 1.8 V power supply and is implemented in a 180 nm CMOS process. Both optimization algorithms were implemented in MATLAB and evaluated using the ZDT1, ZDT2, and ZDT3 test functions. The optimized designs were then simulated using the advance design system (ADS) simulator. The results showed that the MOABC and MOPSO techniques are practical and effective in optimizing LNA design, resulting in better performance than previously published works, with a gain of 21.2 dB and a noise figure of 0.848 dB.

Design and performance analysis of low phase noise LC-voltage controlled oscillator

Voltage controlled oscillator (VCO) offers the radio frequency (RF) system designer a freedom to select the required frequency. Today’s wireless communication system imposes a very stringent requirement in terms of phase noise generated in VCO. This study presents an inductive source degeneration technique to improve the phase noise performance of the inductance-capacitance (LC)-VCO. Double cross-coupled topology has been chosen for the proposed VCO. The p ost layout simulations with the parasitic resistance, inductance, capacitance (RLC) extracted view is carried out with united microelectronics corporations (UMC) 0.18 µm process by spectre simulator of cadence tools. The proposed VCO provides a phase noise of -124.3 dBc/Hz @ 1 MHz. The tuning range obtained is 19.87% with a centre frequency of 2.46 GHz which makes it suitable for industrial, scientific, and medical (ISM) band applications. It consumes a power of 2.10 mW. Also, a good figure of merit of -189 is achieved. The total layout area occupied is 477×545 µ m 2 .

A V‐band digitally controlled low noise variable gain amplifier with 3.5° phase variation in 28‐nm bulk CMOS

AbstractThis paper presents a V‐band digitally controlled low noise variable gain amplifier (LNVGA) in 28‐nm bulk CMOS process. The amplifier includes three stages and the first stage is used to realize wideband high gain and low noise figure (NF). The gain control is implemented in the second and third stages with current steering and split cascode topology, respectively. A source degeneration inductor and a series inductor are introduced to reduce the phase variation in the second stage. The phase response function is analyzed, and the phase reduction of 1.2° is achieved. Moreover, with the combination of these two different topologies, the phase variation can be further reduced. The measurement results show the LNVGA has a peak gain of 16 dB with a 3‐dB bandwidth of 45–59 GHz. The measured gain control range is 0–16 dB in 16 different gain states and the minimum phase variation is 3.5° with power consumption of 23 mW.

CMOS voltage‐controlled oscillator using inductive dual‐balance source degeneration

This study reports a voltage-controlled oscillator (VCO) implemented in a 0.18-μm CMOS process. By utilizing an inductive dual-balance source degeneration (IDSD) technique with a current-reused structure, the proposed VCO improves the phase noise and the power dissipation. The measured output frequency operates at 2.91–3.07 GHz by adjusting a control voltage from 0 to 1.1 V. The measured phase noise of the carrier of 2.94 GHz is −117.44 and −138.34 dBc/Hz at 1- and 10-MHz offsets, respectively. The proposed VCO core consumes 2.38 mW from a supply voltage of 1.1 V. The figures-of-merits (FOMs) of the proposed VCO at 1- and 10-MHz offsets are −183.04 dBc/Hz and −183.94 dBc/Hz, respectively.

-Band Class-B VCO in 22 nm FD-SOI With Inductive Source Degeneration of the Tail Current Source

In this work, a voltage-controlled oscillator (VCO) in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band has been introduced that uses the proposed technique named “inductive source degeneration of the tail current source.” The contribution of this work is that the auxiliary resonator is placed differently than the conventional works so that it leads to a more compact solution without affecting the phase noise (PN). Based on the simulation results, for the same device sizes and power consumption, the proposed Class-B method reduces the PN by 1.5 dB than the conventional one at 1 MHz offset from 24 GHz center frequency. VCO has been fabricated on a die area of 0.026 mm2 in the 22 nm fully depleted silicon on insulator (FD-SOI) technology. The measurement was done in the free-running mode, and the results show a PN of −122.4 dBc/Hz at 10 MHz offset from the center frequency of 23.8 GHz. The power consumption of the VCO core is 14.4 mW with 1 V supply voltage. According to the measurement results, this work achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\text {FoM}_{A}}$ </tex-math></inline-formula> , a figure of merit which considers the VCO core area, of −194.2 dBc/Hz at 10 MHz offset from the center frequency, featuring state-of-the-art among the CMOS VCOs in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band.

An improved cascode common-source LNA with inductive source degeneration for RF applications

This paper presents a novel structure to enhance the power gain (S21) of the conventional cascode common-source (CS) low-noise amplifier (LNA) with inductive source degeneration. The proposed LNA has an extra transistor and a capacitor in comparison with the conventional structure. The additive transistor significantly increases the S21 of the conventional cascode CS LNA with inductive source degeneration with the same DC power consumption (PDC), third-order input intercept point (IIP3), area, and slightly lower noise figure (NF). The utilized capacitor is used to improve the IIP3 of the proposed LNA. The power gain improvement of the proposed LNA has been validated by both theoretical analysis and extensive post-layout simulation results. The proposed and conventional LNAs have been designed in TSMC 180 nm CMOS technology. The post-layout simulation results of the proposed LNA are 2.42 dB NF, S21 of 15.55 dB, and 0.84 dBm IIP3 while consuming 3.2 mW from 1.2 V power supply. The simulated S21 of the proposed LNA is about 2.55 dB (34.2 %) larger than the conventional cascode LNA with the same other performance parameters. Also, the achieved figure-of-merit (FoM) of the proposed LNA is substantially larger than the conventional cascode CS LNA with inductive source degeneration.

Design and analysis of 28 GHz CMOS low power LNA with 6.4 dB gain variability for 5G applications

AbstractA 28 GHz two stage low noise amplifier (LNA) is proposed with envelope detection technique for power reduction (21.62%) and tunable negative feedback capacitor for gain variation in 40 nm CMOS technology. The envelope detection circuit turn‐on the second half of the LNA by the RF signal input received at the first stage. The default gain is increased (31.53%) by the tunable negative feedback capacitor circuit of the LNA with the control voltage from 0 to 1 V. In addition, 6.22 GHz of bandwidth is achieved with the tunable gain from 20.3 dB to 26.7 dB. The first stage of the LNA is designed with the inductive source degeneration for the noise reduction, and the multiple‐gate topology is involved in the second stage to improve the linearity. The third‐order input intercept point and the noise figure of the LNA are −7 dBm and 2.86 dB, respectively. When the second stage is turned‐on and turned‐off the LNA consumes 7.4 mW and 5.8 mW of power, respectively, from the 1 V supply. The proposed LNA requires 0.19 mm2 of core area. The performance of the LNA under process corner variation and temperature variation are analyzed.

A Low-Band Multi-Gain LNA Design for Diversity Receive Module with 1.2 dB NF.

This paper presents and discusses a Low-Band (LB) Low Noise Amplifier (LNA) design for a diversity receive module where the application is for multi-mode cellular handsets. The LB LNA covers the frequency range between 617 MHz to 960 MHz in 5 different frequency bands and a 5 Pole Single Throw (5PST) switch selects the different frequency bands where two of them are for the main and three for the auxiliary bands. The presented structure covers the gain modes from −12 to 18 dB with 6 dB gain steps where each gain mode has a different current consumption. In order to achieve the Noise Figure (NF) specifications in high gain modes, we have adopted a cascode Common-Source (CS) with inductive source degeneration structure for this design. To achieve the S11 parameters and current consumption specifications, the core and cascode transistors for high gain modes (18 dB, 12 dB, and 6 dB) and low gain modes (0 dB, −6 dB, and −12 dB) have been separated. Nevertheless, to keep the area low and keep the phase discontinuity within ±10, we have shared the degeneration and load inductors between two cores. To compensate the performance for Process, Voltage, and Temperature (PVT) variations, the structure applies a Low Drop-Out (LDO) regulator and a corner case voltage compensator. The design has been proceeded in a 65-nm RSB process design kit and the supply voltage is 1 V. For 18 dB and −12 dB gain modes as two examples, the NF, current consumption, and Input Third Order Intercept Point (IIP3) values are 1.2 dB and 16 dB, 10.8 mA and 1.2 mA, and −6 dBm and 8 dBm, respectively.

A +7.6 dBm IIP3 2.4-GHz Double-Balanced Mixer With 10.5 dB NF in 65-nm CMOS

In this brief, an enhanced derivative superposition (DS) method is proposed to increase the third-order input intercept point (IIP3) of double-balanced CMOS active mixers. In the proposed mixer, an auxiliary common-gate transconductor biased in the moderate inversion region with a source inductive degeneration is used in the feedforward AC-coupled path to the main transconductor to generate the third-order intermodulation distortion (IMD3) current. Hence, the overall IMD3 current of the transconductance stage is minimized while optimizing the conversion gain (CG). This auxiliary transconductor also improves the overall NF of the mixer by partially cancelling the output noise voltage. In addition, the current reuse and current bleeding techniques are utilized to further improve the overall performance. As a proof-of-concept, a 2.4-GHz down-conversion mixer with an output bandwidth of 10 MHz is implemented in a 65-nm CMOS process. Measurement results show that the mixer achieves a peak CG of 12.5 dB, a double-sideband (DSB) noise figure (NF) of 10.5 dB, and IIP3 of +7.6 dBm. The circuit consumes 1.2 mW from a 1-V supply and excluding the pads, it occupies a silicon area of 0.2208 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Cryogenic Broadband Sub-1-dB NF CMOS Low Noise Amplifier for Quantum Applications

A cryogenic broadband low noise amplifier (LNA) for quantum applications based on a standard 40-nm CMOS technology is reported. The LNA specifications are derived from the readout of semiconductor quantum bits at 4.2 K, whose quantum information signals are characterized as phase-modulated signals. To achieve broadband input matching impedance and low noise figure, the gate-to-drain capacitance of the input transistor is exploited. The goal is to involve a resistive and capacitive load into the input impedance match of a common-source stage with source inductive degeneration. The capacitive load is created by an LC parallel tank whose resonant frequency is lower than the operating frequency. The achieved non-constant in-band equivalent capacitance is proven to be beneficial to input impedance matching. The resistive part of the load is provided by the transconductance of the cascode stage implicitly. An inductor is added to the gate of the cascode transistor to suppress its noise, and a transformer-based resonator with two resonant frequencies serves as the load of the first stage, thus extending the operating bandwidth. Design considerations for the cryogenic temperature operation of the LNA are proposed and analyzed. The LNA achieves a measured gain ( $S_{21}$ ) of 35 ± 0.5 dB, return loss > 12 dB, and NF of 0.75–1.3 dB across the band (4.1–7.9 GHz), with 51.1-mW power consumption at room temperature, while it shows a measured gain of 42 ± 3.3 dB, and NF of 0.23–0.65 dB with 39-mW power consumption at 4.2 K between 4.6 and 8 GHz. To the best of our knowledge, this is the first report of a cryogenic LNA based on a bulk CMOS process working above 4 GHz showing sub-1-dB NF both at room and cryogenic temperatures.

A two-stage power amplifier design for ultra-wideband applications

In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz based on common source inductive degeneration with an auxiliary amplifier is proposed. In this proposal, an auxiliary amplifier is used to place the 2nd harmonic in the core amplified in order to make up for the gain progression phenomena at the main amplifier output node. Simulation results show a power gain of 16 dB with a gain flatness of 0.4 dB and an input 1 dB compression of about -5 dBm from 3 to 5 GHz using a 1.8 V power supply consuming 25 mW. Power added efficiency (PAE) of around 47% at 4 GHz with 50 Ω load impedance was also observed.

An ESD and Interference-Robust Protection Circuit for Cascode Low-Noise Amplifier in CMOS-SOI Technology

In this paper, we propose a double diode network including an additional stacked diode, which provides robustness against Electrostatic discharge (ESD) and high-frequency interference signals. The proposed stacked diode in the conventional double diode network protects the integrated circuit from instantaneous voltage events by providing an additional current path to the double diode network. Also, it can structurally minimize the parasitic capacitance generated in the diode. The general operating principle and limitation of the conventional double diode network for ESD events and high-frequency interference signals were analyzed and simulated. For experimental verification, a cascode LNA with inductive source degeneration was designed in a 130nm CMOS Silicon-on-insulator (SOI) process for the time-division long-term evolution (TD-LTE) application at the coexistence band. The LNA with the proposed double diode network provides a noise figure of 1.08 dB and a small-signal gain of 18.7 dB at 2.65 GHz (Band 41). And it was measured to be able to protect the internal circuit at 2000 V HBM event, and the RF performances were not affected even with a high-frequency interference signal close to 30 dBm.

Design and analysis of a sleep and wake-up CMOS low noise amplifier for 5G applications

This brief proposes a two-stage cascoded CMOS LNA with common drain envelope detection based power reduction method for the 5G applications of 28 GHz frequency. Dual inductive peaking and stagger tuning techniques are involved to get a 3 dB bandwidth of 2.25 GHz from 26.75 to 29 GHz. Besides, 22 dB of gain is provided by the proposed LNA. Inductive source degeneration helps to reduce the Noise Figure (NF) of the first cascoded stage, and a 2.3 dB of NF is observed in the LNA. The primarily amplified signals from the first cascoded stage are fed to the envelope detector and the second cascoded stage. When the RF signal is received, the envelope detector output will be high, and it turns on the second cascoded stage. In the existing method, the combination of a diode-connected transistor, low pass filter and buffer has been used for the envelope detection. A common drain transistor with an active resistor and capacitor is used in the envelope detection of the proposed method. Here, the power consumption of the LNA is reduced by 25.26% at the sleep mode. The proposed LNA consumes 9.5 mW and 7.1 mW of power from a 1.5 V supply at the active state and sleep state respectively. It requires 0.1235 mm2 of core area in 90 nm technology. Moreover, the behavior of the circuit under process corner variation and temperature variation is analyzed, and Monte–Carlo analysis is performed.

Low-power low-phase noise VCO for 24 ​GHz applications

In this paper, CMOS voltage controlled-oscillator (VCO) with a frequency range of 22.7 ​GHz–27.9 ​GHz is presented. The scheme is modified current-reuse configuration, applicable to 5G applications. In the proposed configuration, the transistors are biased in subthreshold vicinity (VGS ​< ​VTH) to reduce power consumption. The usage of the capacitive feedback technique helps the output voltage to swing over the positive supply voltage and beneath the potential ground. The inclusion of the cross-coupled NMOS transistors with the inductive source degeneration enhance the transconductance and phase noise performance of VCO. The VCO has been implemented using 65 ​nm CMOS technology. The proposed VCO baised with 0.9 ​V and it showed the lowest power consumption of 1.35 ​mW and the lowest phase noise of −117 ​dBc/Hz at the 1 ​MHz offset frequency as compared to conventional results. This circuit also showed wide tuning range of 26.4%, low FOMT of −194.3 ​dBc/Hz, and small area in core die of 0.35 ​mm ​× ​0.35 ​mm. In addition, we have analyzed the mesaured output power spectrum of the proposed VCO using spectrum analyser (Anritsu, MS2760A) whereas the measured output power of the designed VCO is −7.9 dBm at the frequency of 24.5 ​GHz.

A 28-GHz CMOS Down-conversion Mixer with Low-magnetic-coupled Source Degeneration Inductors for 5G Applications

This paper presents a 28-GHz CMOS millimeter-wave down-conversion mixer employing a derivative superposition linearization technique with our proposed low-coupling source degeneration inductors for 5G cellular communication systems to improve the linearity performance of the downconversion mixer. The proposed low-magneticcoupled source degeneration inductors avoid the linearity degradation gap between the schematic design without considering magnetic coupling and the post-layout design with considering magnetic coupling effect due to the source degeneration inductors. The down-conversion mixer with local oscillator buffer is implemented using a 65-nm CMOS technology, and it draws a 21 mA from a 1-V supply voltage. It achieves a gain of 10.1 dB, noise figure below 10 dB, and third-order output intercept point of 19.3 dBm from 26.5 to 29.5 GHz.