Current Mode Logic Research Articles

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

This article describes a 128-Gb/s pulse amplitude-modulation 4-level (PAM-4) transmitter (TX) implemented in a 14-nm CMOS FinFET technology. Equalization is provided by a fully reconfigurable 3-tap baud-spaced feed-forward equalizer (FFE). The TX uses a segmented tailless current mode logic (CML) driver topology. The key architectural and circuit techniques include the thermometer-encoded driver slices, the clock phase selection circuits to perform segment reassignment to different FFE taps, and coarse–fine tuning of the FFE tap weights. The measured energy efficiencies for PAM-4 signaling are 1.33 pJ/b at 128 Gb/s with 1-Vppd output amplitude and 1.0 pJ/b at 112 Gb/s with 0.6-Vppd output amplitude. These results represent the highest data rate and best energy efficiencies reported to date.

A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application

In the present technology development billions of transistors are fabricated on a single chip, which improves the performance of circuits in terms of high data transmission speed and power consumption. This requirement of data transmission speed is achieved with the help of high-speed transceivers. In this paper, we present a high-speed asynchronous wave-pipelined serializer and deserializer (SerDes) transceiver implemented using current-mode logic (CML). This asynchronous transceiver circuit does not require a clock and therefore it saves large amount of power which is consumed in the phase locked loop (PLL) and frequency synthesizer circuits. Further, the proposed design is built using CML which saves more power. CML circuit operates at relatively higher speed as compared to CMOS circuits which helps the circuit to operate at higher data rate. Compared to conventional CML latch, a novel CML latch is proposed in our design to increase the speed. The circuit is implemented in standard CMOS 65-nm technology. The total power consumed by the serializer and deserializer is 9.32[Formula: see text]mW, which is very less as compared to published related works. The proposed asynchronous SerDes transceiver operates at 18.1-Gbps data transmission rate with low power dissipation.

Design of a low-power 12.5Gb/s 1:10 demultiplexer in 0.18μm CMOS*

A low-power 12.5Gb/s 1:10 Demultiplexer (DEMUX) without inductors is designed in 0.18μm CMOS (Complementary metal oxide semiconductor) process. The 1:10 DEMUX includes a high-speed 1:2 DEMUX, two serial low-speed 1:5 DEMUX, a 5 frequency divider and so on. The latch of the high-speed 1:2 DEMUX adopts the CML (Current Mode Logic) structure. The rest of the triggers all use E-TSPC(Extended True Single Phase Clock)structure. In the design of the 5 frequency divider, the logic gate circuit is embedded in flip-flop to improve the work frequency. The post simulated result shows that when the data rate of the input pseudorandom is 12.5Gb/s and the clock frequency is 6.25GHz at a supply voltage of 1.8V, this1:10 DEMUX can work well and the eye diagram of output data is clear. The output swing is 400mV on an external 50 Ohm load and the total power dissipation is 200mW. The die size is 0.64×0.57mm2.

A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-$g_{{m}}$ Cell

This paper presents an area-efficient current-mode-logic (CML)-based divider, with a tunable self-resonant frequency for locking range (LR) extension. Specifically, a negative- $g_{m}$ (NG) cell is inserted between the resonated shunt-peaking inductor and the load resistor to shift the divider’s sensitivity curve (SC), enabling concurrently a higher operating frequency and a wider LR. We also use the injection-locking concept, together with a graphical phasor diagram with the frequency-phase information, to systematically explain the LR-extension mechanism. Prototyped in a 65-nm CMOS, the divider occupies a tiny active area of 0.0018 mm2. The measured LR is 153% (4–30 GHz) while consuming 4.06–4.28 mW at 30 GHz under a single 1.2-V supply. The performance corresponds to two figure of merits: FOM $_{\mathbf {Pdc}}$ of 25.5 dB and FOM $_{P}$ of 71.5, both compare favorably with the state of the art.

A Novel 19.6 GHz, High Speed and Low Power Dual Modulus 2/3 Design based on Implication Logic Cells in 130nm CMOS Technology

In this paper, we describe the merging technique and non-traditional logics for design of a divide - (÷) by-2/3 design. The proposed circuit of design consumes a smaller amount of power than true single - phase clock (TSPC), Current - mode logic (CML) logic styles and operates faster than enhanced TSPC(ETSPC) designs. By theoretical analysis, one can conclude that the switching power and propagation delay of the proposed circuit is less than that of conventional ÷ - by - 2/3 prescaler. The Power consumption of proposed circuit is reduced by 39% as compared with the conventional design. The design is realised in 130 nm CMOS process at power consumption of 8μW under 0.8V of a supply voltage, andthe maximum working frequency reaches up to 19.6 GHz.

An improved current mode logic latch for high‐speed applications

SummaryIn this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.

A Current-mode Logic Driver with Two-tap Pre-emphasis using Reconfigurable Capacitive Peaking for -12.3 dB Insertion Loss

This paper proposes a 10-Gb/s output driver based on Current-Mode Logic (CML) driver with 2-tap including pre-emphasis and de-emphasis method by using reconfigurable capacitive peaking. The proposed is implemented in 55-nm CMOS process with 1.2 V supply. The proposed output driver can compensate for insertion loss -12.3 dB just with 2-tap and controlling the number of capacitor that is able to change pre-emphasis gain. Additionally, the de-emphasis gain is able to be changed by using 2-tap current source. Thus, the proposed achieves about 3.8 times higher gain than the conventional CML driver and evenly reduces power consumption up to 56.32% compared the conventional CML driver with the same of number of taps.

Fabrication Cost Analysis for Contactless 3-D ICs

The manufacturing cost of contactless 3-D circuits with inductive links is explored for the first time. The high-volume manufacturing (HVM) cost of contactless 3-D ICs is modeled by considering the on-chip inductor area and other important parameters, such as the coupling efficiency, which depend upon specific steps of the fabrication process. Inductive links based on current mode logic (CML) transceivers are simulated across a number of integration scenarios in a commercial 65-nm CMOS technology process, thereby evaluating the cost of these manufacturing options for performance and power objectives. Assuming a 10 Gb/s data rate, the power and area of the inductive link are determined for wafer-to-wafer and die-to-wafer integration and communication distances in the range of 5 $\mu \text{m}$ (face-to-face) to 120 $\mu \text{m}$ (face-to-back). An HVM cost estimation for each investigated inductive link scheme is provided for these integration approaches. Additional processing steps attributed to 3-D integration increase the aggregate cost by 2.5%–4.5% for a case study of a three-tier stack, compared to a conventional 2-D process. Moreover, the yield is explored for each integration approach considering the inductor area for contactless 3-D ICs.

A 10-Gb/s 20-ps Delay-Range Digitally Controlled Differential Delay Element in 45-nm SOI CMOS

This brief presents a 4-bit digitally controlled differential delay element (DCDE) with high-speed and high-resolution capability, two challenging requirements in the design of delay elements. Two input bits, inside the differential current-mode logic (CML) DCDE, regulate its bias current and the resistive load, while the other two bits configure the output capacitive load enabling the presented DCDE to achieve a phase shift of 20 ps and an average resolution of 1.25 ps. Designed in 45-nm silicon-on-insulator (SOI) CMOS, the DCDE dissipates 4 mW of power under maximum biasing condition and can operate up to 10 Gb/s while adding only 0.6 ps of root-mean-square jitter to the delayed input. To the best of authors knowledge, the designed DCDE is the first 4-bit low-jitter 10-Gb/s variable-load CML DCDE offering a time resolution of 1.25 ps, making it a suitable candidate for high-speed and high-resolution applications.

A Ku-band dual control path frequency synthesizer using varactorless Q-enhanced LC-type VCO

This study focused on the design principle and implementation of a high-frequency, wide-range frequency synthesizer by using a dual control path phase-lock loop (PLL) and a varactorless oscillator controlled by inductive–capacitive (LC-type) voltage (i.e., a voltage-controlled oscillator, VCO). Without a varactor in the LC tank, the tuned-transducer oscillator with Q-enhanced functionality can easily arrive at the requirements of high-frequency wide-range low-noise operations. We utilized a difference tuned varactorless VCO to create two different KVCOs and applied it to a dual control path PLL architecture to obtain wide tuning range and more favorable phase noise. In addition, a high-speed current-mode logic divider was employed given its high speed (because of the use of a transformer inductor), extremely high operation frequency, and wide-range. The proposed PLL was assembled using the standard 0.13-μm CMOS technology on a 0.95 × 1.05 mm2 chip. The PLL dissipated 40 mW at a 1.2 V supply. The measurement of phase noise at 17.64 GHz was − 98.12 dBc/Hz at a 1 MHz offset.

A compact 0.045–2.3 GHz frequency synthesizer with a wide tuning range low phase noise VCO for software defined radios

A compact 0.045–2.3 GHz wideband fractional-N frequency synthesizer (FS) for software defined radios (SDR) applications is presented in this paper. Based on a single phase locked loop (PLL) that employs one integrated inductor-capacitor voltage controlled oscillator (VCO), the proposed FS can provide a wide operating frequency range. The VCO adopts an optimized circular inductor to mitigate the phase noise degradation caused by the high VCO gain. The in-band phase noise is optimized by employing current mode logic dividers and true single phase clock dividers. The PLL provides the differential outputs ranging from 2.3 to 4.6 GHz and the 0.045–2.3 GHz quadrature local oscillator signals are generated by the following divider chain. The proposed FS is implemented in TSMC 180 nm RFCMOS process and provides a phase noise performance less than − 116 dBc/Hz at 1 MHz offset. The maximum power consumption is 54 mW. The die size including pads and I/O is 1.92 mm2 with an active core area of 1.13 mm2. This proposed circuit has the great potential for SDR applications.

Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication

The conventional MOS current mode logic (MCML)-based multiplexer needed for serializer application has various limitations, such as low voltage-swing, substantial power consumption, and large area overhead. In the circuit arrangement of a serializer using the MCML-based mux-tree concept, the output of one mux at any stage is used to feed another mux at the next stage through some latch circuits, which are basically used for timing synchronization giving away penalty in terms of delay and area. The increase in number of stages of the Serializer may lead to further reduction in output swing (if common mode is not properly set), thereby causing signal integrity issues and finally loss of data. To address the same, a latency combined current mode multiplexer incorporating pMOS-based dual cross-coupled latch circuit is unearthed in this paper to further outline an area and energy efficient high-speed serializer capable of maintaining uniform peak-to-peak swing and signal quality at differential outputs. The simulations of new serializer are performed for 90-nm CMOS in the Cadence Virtuoso platform, where the average power and delay are found to be $471.6~\mu \text{W}$ and 93.9 ps, respectively, to provide a power delay product of 43.8 fJ only at a power supply of 1 V. An improved output swing of 904 mV is also noticed along with a data rate of 50 Gb/s and a BER of <10−12. The entire design is proved to be a robust one after simulating it through Monte Carlo at five different process corners and also validated at lower process nodes such as 28-nm UMC.

A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET

This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-rate architecture with a three-tap feed-forward equalizer (FFE). Key features of the TX include a 1-UI pulse-generator-based 4:1 serializer combined with a current-mode logic (CML) driver, low-power data-serializing paths, an output pad-network using a multi-segment $\pi $ -coil for bandwidth co-optimization together with ESD diodes, sub-80-fs resolution duty-cycle detector/corrector (DCD/DCC) and quadrature-error detector/corrector (QED/QEC) circuits, and a hybrid LC -phase-locked loop (PLL) with quadrature clock distribution circuits. The TX operating at 112 Gb/s in PAM-4 modulation consumes 232 mW from 1- and 1.5-V supplies, achieving an 2.07 pJ/b energy efficiency. The TX front end occupies an area of 0.0302 mm2.

DESIGN OF THE HIGH SPEED AND RELIABLE SOURCE COUPLED LOGIC MULTIPLEXER

As the rapid growth of the VLSI technology over the years the momentum shifts towards the low power and high speed portable electronic devices respectively. Power consumption is one critical aspect which may leads to decreases the reliability and performance of the portable devices. the main aim of this work is to design a low power and high speed Source Coupled Logic (SCL) multiplexer and its analytical model. This circuits can be widely used in mixed signal circuits and high resolution optical fiber links.the proposed circuit was implemented in CMOS 45 nm technology using cadence virtuoso by using industrial technology libraries. And we compared its performances with the existed configurations of the multiplexers with different technology nodes.

Prognosis of Manufacturing of a Two-Level Current-Mode Logic Gate in Latch Based on Heterostructures to Increase Density of their Elements with Account Miss-Match Induced Stress and Porosity of Materials on Technological Process. On Approach for Optimization of Manufacturing

Prognosis of Manufacturing of a Two-Level Current-Mode Logic Gate in Latch Based on Heterostructures to Increase Density of their Elements with Account Miss-Match Induced Stress and Porosity of Materials on Technological Process. On Approach for Optimization of Manufacturing

Design of CNTFET-based Current-mode Multi-input m:3 (4 ≤ m ≤ 7) Counters

ABSTRACT This paper presents current-mode multi-input m:3 (4 ≤ m ≤ 7) counters based on carbon nanotube FET (CNTFET). Two different approaches are considered for these designs. In the first approach, a current mode m:3 (4 ≤ m ≤ 7) counter is achieved by means of current-mirrors in the output paths. The second proposed current-mode m:3 (4 ≤ m ≤ 7) counter is designed without requiring current-mirrors. This leads to lower number of transistors and lower power dissipation in comparison with the first approach. All of the designs are simulated using the Stanford CNTFET HSPICE model at 32 nm feature size. The results indicate that the second proposed designs are consistently faster and consume lower power than the first designs. Therefore, our PDP figure is improved by 35%, 30%, 36% and 26% as compared to those of current-mode logic (CML) counter 4:3, CML counter 5:3, CML counter 6:3 and CML counter 7:3, respectively.

A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3–283.7 GHz and a phase noise of −53.5 dBc/Hz at 100 kHz (in band) and −78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μ m2 excluding probing pads.

A power scalable 2–10 Gb/s PI-based clock data recovery for multilane applications

This paper presents a power scalable clock data recovery (CDR) suitable for multilane and multirate applications. To make the power consumption scale with the data rate and guarantee appropriate edge overlaps for the phase interpolation, a delay-locked loop-based global biasing strategy is proposed to automatically adjust the bandwidth of the current-mode logic buffers and phase interpolator (PI). The I, Q clocks are generated by a local clock conditioner, which employs an open-loop voltage-controlled delay line to produce the evenly spaced multiple phases and adopts a two-stage timing averaging to correct the duty cycle distortion and I, Q mismatch. Additionally, a phase-compensating technique is adopted in the PI to optimize its linearity. Implemented in a 65-nm CMOS process with an area occupation of 0.12 mm2, the presented CDR can operate from 2 to 10 Gb/s with a scalable power consumption from 11 to 42 mW. When it operates at 10 Gb/s, the maximum tolerable amplitude of the sinusoidal jitter at 50 MHz is 0.52 UIpp, and the total jitter of the recovered clock is 16.6 ps at a BER of 1e-12.

An energy efficient PVT aware novel CML-TG based Mux-Latch circuit Serializes high rate data

The high speed wireline communication suffers from a lot of signal quality issues such as jitter and swing, which eventually leads to higher probability of data loss. As the current mode multiplexer, being the integral cell of any transceiver circuit guides to Serialize data in high rate, its arrangement is of utmost importance. This work explores a novel configuration of multiplexer embedded with cross-coupled NMOS latch after integrating the Transmission Gate (TG) principle with the MOS Current Mode Logic (MCML). The proposed configuration reads an average power, delay and power-delay product (PDP) of as tiny as 135.7 μW, 20.16 ps and 2.736 fJ, respectively when simulated for 90 nm CMOS using Cadence Virtuoso at 10 GHz switching frequency and 1 V power supply. The process variation is performed at different corners through Monte-Carlo runs with ‘no skew’ and ‘5% process skew’ variation at both pre-layout and post-layout to prove the robustness of the proposed Mux-Latch, which is employed to tender a new low gate count and energy efficient variation aware Serializer circuit capable of offering a data rate of as high as 50 Gbit/s. The entire circuit is also validated at lower technology nodes like 28 nm UMC.

Design of a high radiation-hard driver for Mach–Zehnder Modulators based high-speed links for hadron collider applications

Abstract This work presents a design of a driver in 65 nm TSMC technology for a custom MZM designed to withstand non-ionizing energy losses (NIEL) of up few 1016 n/cm 2 and up to 500 Mrad total ionization doses (TID). The design of the driver is optimized for a TID exceeding 500 Mrad, for a target bit rate of 10 Gbps. The driver uses a CML (Current Mode Logic) architecture. A cascode architecture is adopted in the last stage to increase the driving voltage. Two driver designs have been implemented, the largest sizing 347 × 180 μ m 2 layout area and about 170 mW predicted power consumption at 500 Mrad. The ASIC has been submitted to foundry in May 2018.