Fabrication Cost Analysis for Contactless 3-D ICs

Abstract

The manufacturing cost of contactless 3-D circuits with inductive links is explored for the first time. The high-volume manufacturing (HVM) cost of contactless 3-D ICs is modeled by considering the on-chip inductor area and other important parameters, such as the coupling efficiency, which depend upon specific steps of the fabrication process. Inductive links based on current mode logic (CML) transceivers are simulated across a number of integration scenarios in a commercial 65-nm CMOS technology process, thereby evaluating the cost of these manufacturing options for performance and power objectives. Assuming a 10 Gb/s data rate, the power and area of the inductive link are determined for wafer-to-wafer and die-to-wafer integration and communication distances in the range of 5 $\mu \text{m}$ (face-to-face) to 120 $\mu \text{m}$ (face-to-back). An HVM cost estimation for each investigated inductive link scheme is provided for these integration approaches. Additional processing steps attributed to 3-D integration increase the aggregate cost by 2.5%–4.5% for a case study of a three-tier stack, compared to a conventional 2-D process. Moreover, the yield is explored for each integration approach considering the inductor area for contactless 3-D ICs.