Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication

Abstract

The conventional MOS current mode logic (MCML)-based multiplexer needed for serializer application has various limitations, such as low voltage-swing, substantial power consumption, and large area overhead. In the circuit arrangement of a serializer using the MCML-based mux-tree concept, the output of one mux at any stage is used to feed another mux at the next stage through some latch circuits, which are basically used for timing synchronization giving away penalty in terms of delay and area. The increase in number of stages of the Serializer may lead to further reduction in output swing (if common mode is not properly set), thereby causing signal integrity issues and finally loss of data. To address the same, a latency combined current mode multiplexer incorporating pMOS-based dual cross-coupled latch circuit is unearthed in this paper to further outline an area and energy efficient high-speed serializer capable of maintaining uniform peak-to-peak swing and signal quality at differential outputs. The simulations of new serializer are performed for 90-nm CMOS in the Cadence Virtuoso platform, where the average power and delay are found to be $471.6~\mu \text{W}$ and 93.9 ps, respectively, to provide a power delay product of 43.8 fJ only at a power supply of 1 V. An improved output swing of 904 mV is also noticed along with a data rate of 50 Gb/s and a BER of <10−12. The entire design is proved to be a robust one after simulating it through Monte Carlo at five different process corners and also validated at lower process nodes such as 28-nm UMC.