Current Mode Logic Research Articles

Design of an Inductor-Less 72-GHz 2:1 CMOS CML Frequency Divider With Dual-Core VCO

This brief presents the modeling and design of a static current-mode logic, divide-by-2 frequency divider for mm-wave frequency synthesis. An optimized design procedure based on the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$RC$ </tex-math></inline-formula> delay model and insights into the nonlinear mixing conversion gain of the injection-locking model are presented and leveraged towards the design of an inductor-less 28-nm CMOS prototype that achieves 72 GHz maximum input frequency and power-delay product of 21.5 fJ. Performance can be tuned to 66 GHz and 16.9 fJ, respectively, via lowering the supply voltage. In addition to standalone measurements with an off-chip input signal, a fundamental-frequency dual-core voltage-controlled oscillator provides on-chip and realistic input signal generation.

Low Power Linear Feedback Shift Register Using DY-CML

A Linear Feedback Shift Register (LFSR) is a sequential shift register that cycles through a succession of binary values in a pseudo-random way using combinational logic. Pseudo-noise sequences, whitening sequences, and fast digital counters are some of the applications of LFSR. The design of a 4-bit LFSR employing CMOS, MOS Current-Mode Logic (MCML), and Dynamic Current-Mode Logic (DY-CML) approaches are shown in this paper. MCML has low power consumption and better performance. The disadvantage of MCML approach is that it has more static power dissipation due to the constant current source. In order to solve the issues of MCML approach, the DY-CML with a dynamic current source is used to design the LFSR. All designs are simulated using the Mentor graphics tool, which uses 90nm technology. This paper also includes a comparison of LFSR’s in terms of power, delay, and transistor count.

On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates

Dynamic positive feedback source-coupled logic (D-PFSCL) gates are used as a low power alternative in mixed signal applications over static positive feedback source coupled logic (PFSCL) gates. In this paper, transmission gates (TG) are included in the dynamic positive-feedback source coupled logic (D-PFSCL) architecture. The proposed scheme allows implementation of logic functions which in existing schemes is restricted to NOR/OR only or three input AND/OR only realization forms. The significant reduction in the number of stages, dynamic current sources and self-timed buffer with proposed scheme leads to efficient D-PFSCL design in comparison to the existing ones. Simulations using PTM 65 nm technology node at frequency of 1 GHz are performed. A maximum improvement of 40.8%, 73% and 97% in delay, dynamic power consumption and EDP respectively is been observed for D-PFSCL exclusive-OR(XOR2) gate implemented using proposed scheme with respect to existing D-PFSCL schemes. Further, a study on the trade-off between power dissipation and frequency of operation is included for the completeness.

A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36&#x0025;, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate <inline-formula> <tex-math notation="LaTeX">$&lt; 1\text{E}$ </tex-math></inline-formula>-10 with a power efficiency of 4.75 pJ/bit.

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces

Separate inverter-based summers for each eye are introduced into the decision feedback equalizer (DFE) of a single-ended four-level amplitude modulation (PAM-4) receiver for memory interfaces. The summers increase the input swing of the slicers while maintaining the advantages of inverter-based amplifiers with higher gain and lower power consumption than current-mode logic (CML) amplifiers. The high-gain summer can improve clock-to-Q delays of slicers in the PAM-4 DFE without increasing the power consumption of the slicers. This can alleviate the timing constraint that the DFE must meet to respond correctly to the previous data. The non-linear gain of the inverter-based structure can be ignored by using separate paths depending on each eye. A prototype chip was fabricated in a 65 nm CMOS process. At 24 Gb/s, the DFE can achieve a bit error rate (BER) of 10^-12 with an eye width of 100 mUI with -7.3 dB insertion loss at Nyquist frequency and the power efficiency of 0.73 pJ/b.

Track and Hold Amplifier Investigation for 100-GHz Bandwidth, 200-GS/s ADC Front Ends

We report on the track and hold amplifier (THA) topology choice and design details of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> time-interleaved 200-GS/s SiGe BiCMOS ADC front end with a measured SNDR > 25 dB up to 63 GHz, and with a large signal bandwidth of 58 GHz when subsampling at 5 GS/s. We show that by replacing the current-mode-logic (CML) MOS switch with a quasi-CML switch and increasing the tail current, a THA with a measured small-signal bandwidth of 101 GHz is obtained in the same 55-nm SiGe BiCMOS technology. The ADC front end bandwidth could thus be further improved at the same sampling rate.

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Now a days, MOS Current Mode Logic (MCML) has emerged as a better alternative to Complementary Metal Oxide Semiconductor (CMOS) logic in digital circuits. Recent works have only traditional logic gates that have issues with information loss. Reversible logic is incorporated with MOS Current Mode Logic (MCML) in this proposed work to solve this problem, which is used for multiplier design, D Flip-Flop (DFF) and register. The minimization of power and area is the main aim of the work. In reversible logic, the count of outputs and inputs is retained as the same value for creating one-to-one mapping. A unique output vector set can be generated for each input vector set and information loss is also prevented. In reversible MCML based multiplier, reversible logic full adder is utilized to minimize the area and power. D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register. The proposed reversible MCML multiplier attains average power of 0.683~mW, Reversible MCML based DFF achieves 0.56 μW and Reversible MCML based 8-bit register attains 04.04 μW. The result shows that the proposed Reversible MCML based multiplier, Reversible MCML based D flip-flop and Reversible MCML based register achieves better performance in terms of current, power dissipation, average power and area.

A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

A novel SCA-resilience flip-flop design utilizing the current mode logic based on the three-independent-gate field effect transistors

A novel SCA-resilience flip-flop design utilizing the current mode logic based on the three-independent-gate field effect transistors

A Low Spur and Low Jitter Quadrature LO-Generator Using CML Inductive Peaking Technique for WLAN Transceiver

The demand for a local oscillator (LO) signal of high quality and integrity in local area network (WLAN) communication is growing with the increasing date rate. The LO signals for high data rate WLAN applications are desired to not only have proper shape waveforms and adequate voltage amplitude but also to achieve relatively stable and clean outputs with low phase noise and low spur. Fractional-N frequency planning is critical for a quadrature LO-generator, which is achieved by a single-sideband (SSB) mixer and multiple dividers since it can avoid the frequency pulling and alleviate the self-mixing and DC offset issues, while spur levels are easily increased due to harmonic mixing, imbalance, and leakage of the SSB mixer. This article proposes a simple and innovative quadrature LO-generator, which adopts a current-mode-logic (CML) inductive peaking (IP) circuit to improve phase noise and suppress spurious tones. Four types of LO delivery methods using IP circuits are proposed and compared. Among four methods, the CML-IP circuit presents the optimum performance for driving long wires of multi-mm length. Instead of previous digital spur cancellation, the CML-IP circuit achieves higher spur suppression, lower jitter, and a greater figure of merit (FoM). The quadrature LO-generator can be configured to either VCO mode or bypass mode supporting external VCO input. Implemented in 55 nm CMOS technology, the proposed quadrature LO-generator achieves −52.6 dBc spur suppression, −142 dBc/Hz phase noise at 1 MHz offset at the 4.8 GHz frequency, and −271 FoM. Furthermore, the quadrature LO-generator occupies an active area of 0.178 mm2 and consumes 23.86 mW.

Design of Linear Feedback Shift Register for Low Power Applications

This paper presents the design &amp; implementation of the Linear Feedback Shift Register (LFSR) using the Mentor Graphics tool in 90nm technology. LFSR’s have a wide variety of applications. They are used in pseudo-random variety generation, whitening sequences and pseudo-noise sequences. MOS current-mode logic (MCML) and Dynamic current-mode logic (DYCML) are employed to design an LFSR. MCML is widely used in high-speed applications and these MCML circuits are based on current steering logic. The advantages of the MCML method are that they have high noise immunity due to their differential nature of inputs. The disadvantage of MCML approach is static power dissipation. To overcome these issues of MCML logic, Dynamic CML logic is used. Its advantages include low static power dissipation and high performance. This paper shows the comparison results of CMOS, Dynamic CML and MCML designs in terms of delay, power and transistor count.

Low-power and low glitch area current steering DAC

A 12-bit partial segmented current steering digital to analog converter (DAC) with low glitch area, power consumption, and integral nonlinearity (INL) error is proposed in this work. The cause of the glitch area and its possible solutions are explored. A current-mode logic (CML) latch with reduced output swing (Vdd to slightly below threshold voltage) is used at the input to the differential switch which reduces the glitch area (also known as glitch energy) significantly to 0.25 pVs. Further, this latch is used in the digital block of the proposed DAC to reduce the area and power requirement of the overall design. A dummy switch is used at the output of the differential switch to diminish effect of charge feedthrough at the output node of a current steering DAC. It also helps in the reduction of minimum allowable voltage headroom as compared to conventional double cascode structure and reduction of total power consumption to 9.1 mW operating at 200 MHz. The design and simulation of current steering DAC are performed in a 0.18 μm standard CMOS technology library using Cadence Virtuoso tool with a supply voltage of 1.8 V.

Analysis and design of low power wideband programmable frequency divider in 0.13-μm SiGe BiCMOS technology

In this paper, a newly analytical method is proposed for the design of programmable frequency dividers. The more accurate transfer function of the current mode logic (CML) stage is used to analyze the injection-locking behavior models of the dual-modulus prescaler, and the general analytical expressions of the locking range of the prescaler are derived. Based on the analytical expressions that can be calculated using device-level circuit parameters obtained through DC and AC simulations, the dual-modulus prescaler design can be optimized quickly and accurately, thereby extending the frequency-division range of the programmable frequency divider. The proposed analytical method is verified by the measured results of the 2–22 GHz programmable divider, fabricated in 0.13-μm SiGe BiCMOS technology. By using heterojunction bipolar transistors (HBTs) in the dual-modulus prescaler and metal–oxidesemiconductor field-effect transistors (MOSFETs) in the pulse and swallow counters, the proposed programmable divider achieves the lowest power consumption of 63.3 mW and the best FOMT compared with previously works.

0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

Power and area‐efficient static current mode logic frequency divider in 180‐nm complementary metal‐oxide‐semiconductor technology

AbstractThis paper presents power and area optimized, high‐speed metal‐oxide‐semiconductor (MOS) current mode logic (MCML)‐based frequency dividers. Each differential pair in the divider is sized separately to minimize the overall power consumption. The divide‐by‐2 frequency divider has been realized in a 180‐nm complementary MOS (CMOS) process technology, and postlayout simulation results show that the proposed frequency divider can work up to an operating frequency of 18.8 GHz in the worst‐case process corner with a maximum power dissipation of 1.715 mW under 1.8‐V supply. It gives a bandwidth of 19.9 GHz which ranges from 1 to 20.9 GHz. The divider occupies a 0.106 × 0.09 mm2 area. The performance corresponds to the figure of merit (FoM) of 43.61 dB. The same optimized latches and two EX‐OR gates are used to design a divide‐by‐5 frequency divider that is also realized in 180‐nm CMOS process technology. The postlayout simulation results show that the proposed divide‐by‐5 frequency divider can faithfully work up to an operating frequency of 12.12 GHz in worst‐case process corner with an excellent power head performance. The maximum power dissipation of the core circuit is 1.39 mW under 1.8‐V supply. It occupies a 0.166 × 0.116 mm2 area. The performance corresponds to the FoM of 26.56 dB which compares favorably with the state of the art.

Prototype of simultaneous bidirectional data-transmitter in 65 nm CMOS

This article presents a design and implementation of an I/O circuit block capable of simultaneous bidirectional data-transmission in CMOS integrated circuits. Merging data-transmitter and receiver into common bonding pad is feasible not only to reduce the number of transmission lines from a considerable number of chips, but also to realize more area-efficient data handling in consequence of flexible inter-chip communication. This feature is attractive from the viewpoint of detector systems in high energy experiments, in which reducing materials such as cables from silicon trackers in inner vertex layers is of major importance to suppress multiple-scattering and to achieve good overall detector performances. The circuit block presented here is designed on the basis of a current subtraction circuit and two distinct current-mode logic drivers. Its principle is also applicable to widely-used low-voltage differential signal drivers and easy for process migration. The prototype chip was fabricated in a 65 nm CMOS technology. Working principle has been demonstrated in preliminary laboratory testing.

An efficient 70 GHz divide‐by‐4 CMOS frequency divider employing low threshold devices

The idea to use a lower threshold, but slightly slower transistor over the fastest transistor type for large-signal circuits is presented with experimental verification for a compact divide-by-4 true single phase clock (TSPC) frequency divider. The use of the lowest threshold PMOS devices resulted in self-resonance frequencies of 41.7, 56, and 60 GHz at supply voltages of 0.5, 0.8 and 0.9 V, respectively. Compared to a divider of the same architecture in the same technology, but with higher threshold voltage devices, this corresponds to improvements of 67%, 33% and 27%, respectively. Power consumptions of 26 and 355 μW were measured for a 20 GHz and a 70 GHz input signal for supply voltages of 0.5 and 0.9 V, respectively. The best knowledge of the authors, these results are the best reported to date for TSPC divider architecture, and they compete with state of the art for inductorless current-mode logic dividers.