Solid-phase Crystallized Polycrystalline Silicon Research Articles

Synthesis and characterization of large-grain solid-phase crystallized polycrystalline silicon thin films

n-type polycrystalline silicon (poly-Si) films with very large grains, exceeding 30 μm in width, and with high Hall mobility of about 71.5 cm2/V s are successfully prepared by the solid-phase crystallization technique on glass through the control of the PH3 (2% in H2)/SiH4 gas flow ratio. The effect of this gas flow ratio on the electronic and structural quality of the n-type poly-Si thin film is systematically investigated using Hall effect measurements, Raman microscopy, and electron backscatter diffraction (EBSD), respectively. The poly-Si grains are found to be randomly oriented, whereby the average area weighted grain size is found to increase from 4.3 to 18 μm with increase of the PH3 (2% in H2)/SiH4 gas flow ratio. The stress in the poly-Si thin films is found to increase above 900 MPa when the PH3 (2% in H2)/SiH4 gas flow ratio is increased from 0.025 to 0.45. Finally, high-resolution transmission electron microscopy, high angle annular dark field-scanning tunneling microscopy, and EBSD are used to identify the defects and dislocations caused by the stress in the fabricated poly-Si films.

Charge carrier transport in boron doped poly-Si

The influence of the used substrate and the boron doping concentration of the charge-transport properties of solid-phase crystallized polycrystalline silicon (poly-Si) is explored. The samples were characterized using temperature dependent transport measurements to determine mobility, carrier concentration, and conductivity. While Arrhenius plots of the hole concentration cannot be used to determine the position of the Fermi energy, a detailed analysis of the temperature dependent carrier concentration shows a Meyer–Neldel and an anti-Meyer–Neldel rule. Charge transport in poly-Si on SiN coated Borofloat glass with a boron concentraion [B] < 1016 cm–3 is limited by phonon scattering. On the other hand, for all poly-Si samples on Corning glass and poly-Si on SiN coated Borofloat glass with [B] > 1016 cm–3 charge-carrier transport is governed by thermionic emission over potential barriers. The data are discussed in terms of the Baccarani transport model.

A Simple Method to Grow Thermal <inline-formula> <tex-math notation="TeX">${\rm SiO}_{2}$ </tex-math></inline-formula> Interlayer for High-Performance SPC Poly-Si TFTs Using <inline-formula> <tex-math notation="TeX">${\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Gate Dielectric

A simple method is proposed to grow thermal SiO2 interlayer when performing solid-phase-crystallized (SPC) process. By employing such interlayer between SPC polycrystalline silicon channel and Al2O3 gate dielectric, highperformance SPC thin-film transistors (TFTs) with field effect mobility of 67.80 cm2V s-1 and ON/OFF ratio of 2.31 × 108 at Vds = -0.1 V are achieved due to the superior interface quality and improved grain boundaries by the incorporation of excess Si interstitials. The TFT with interlayer also exhibits good reliability under negative bias temperature stress test.

Hydrogen passivation of polycrystalline silicon thin films

The influence of post-hydrogenation on the electrical and optical properties of solid phase crystallized polycrystalline silicon (poly-Si) was examined. The passivation of grain-boundary defects was measured as a function of the passivation time. The silicon dangling-bond concentration decreases with increasing passivation time due to the formation of Si-H complexes. In addition, large H-stabilized platelet-like clusters are generated. The influence of H on the electrical properties was investigated using temperature dependent conductivity and Hall-effect measurements. For poly-Si on Corning glass, the dark conductivity decreases upon hydrogenation, while it increases when the samples are fabricated on silicon-nitride covered Borofloat glass. Hall-effect measurements reveal that for poly-Si on Corning glass the hole concentration and the mobility decrease upon post-hydrogenation, while a pronounced increase is observed for poly-Si on silicon-nitride covered Borofloat glass. This indicates the formation of localized states in the band gap, which is supported by sub band-gap absorption measurments. The results are discussed in terms of hydrogen-induced defect passivation and generation mechanisms.

Charge transport in polycrystalline silicon thin-films on glass substrates

Charge carrier transport in solid-phase crystallized polycrystalline silicon (poly-Si) was investigated as a function of the deposition temperature, Td, the amorphous starting material and the used substrates. The samples were characterized using temperature dependent transport measurements to determine the carrier concentration, mobility, and conductivity. Samples prepared on a-SiN:H covered borofloat glass exhibit a low carrier concentration that is independent of Td. In these samples, charge transport is dominated by intra-grain scattering mechanisms. In contrast, when poly-Si is prepared on corning glass, the carrier concentration shows an inverted U-shape behavior with increasing deposition temperature. The Hall mobility is thermally activated, which is consistent with thermionic carrier emission over potential energy barriers. The change of the activation energy with experimental parameters is accompanied by a large change of the exponential prefactor by more than 4 orders of magnitude. This is indicative of a Meyer-Neldel behavior. Moreover, at low temperatures, the conductivity deviates from an activated behavior indicating hopping transport with a mean hopping distance of ≈140 Å and an energy difference of ≈82 meV between the participating states. To derive insight into the underlying transport mechanisms and to determine information on barrier energy heights and grain-boundary defect-densities, the experimental data were analyzed employing transport models for polycrystalline materials.

On the Effect of the Amorphous Silicon Microstructure on the Grain Size of Solid Phase Crystallized Polycrystalline Silicon

AbstractIn this paper the effect of the microstructure of remote plasma‐deposited amorphous silicon films on the grain size development in polycrystalline silicon upon solid‐phase crystallization is reported. The hydrogenated amorphous silicon films are deposited at different microstructure parameter values R* (which represents the distribution of SiHx bonds in amorphous silicon), at constant hydrogen content. Amorphous silicon films undergo a phase transformation during solid‐phase crystallization and the process results in fully (poly‐)crystallized films. An increase in amorphous film structural disorder (i.e., an increase in R*), leads to the development of larger grain sizes (in the range of 700–1100 nm). When the microstructure parameter is reduced, the grain size ranges between 100 and 450 nm. These results point to the microstructure parameter having a key role in controlling the grain size of the polycrystalline silicon films and thus the performance of polycrystalline silicon solar cells.

Influence of the absorber doping for p-type polycrystalline silicon thin-film solar cells on glass prepared by electron beam evaporation and solid-phase crystallization

A systematic investigation of the influence of the absorber doping on the performance of planar, p-type, evaporated, solid-phase crystallized polycrystalline silicon thin-film solar cells on glass is presented. It is found that the optimum Suns-Voc parameters (open-circuit voltage and pseudo fill factor) are achieved at intermediate absorber doping of Nabs∼1–2 × 1017 cm−3, while high short-circuit currents are achieved at the lowest absorber doping of Nabs ≤ 6 × 1015 cm−3. Since the short-circuit current is the dominating factor to achieve high conversion efficiencies for evaporated polycrystalline silicon cells, the maximum pseudo efficiencies are achieved at very low absorber doping. The Suns-Voc characteristics of lightly doped cells can be adequately described by a modified two-diode model with n1=1 and n2≈1.5, which is in contrast to the value of 2 for n2 commonly quoted in the literature. PC1D modeling demonstrates that such a low ideality factor for space charge region recombination can be modeled by a single trap energy level located at ∼0.18 eV away from midgap. Although the achievable short-circuit current densities and the conversion efficiencies can be higher for textured cells, planar cells are chosen intentionally to allow accurate modeling and extraction of relevant material parameters, such as minority carrier diffusion length.

Embedded NVM Devices with Solid-Phase Crystallized Poly-Si Film on a Glass Substrate for System-on-Panel Applications

Embedded nonvolatile memory (NVM) devices with solid-phase crystallized polycrystalline silicon (poly-Si) films and an oxide–nitride–oxynitride (ONOn) stack structure on a glass panel were fabricated and investigated for system-on-panel applications. Memory-in-pixel and memory blocks are expected to be integrated in display panels as the integration of display systems progresses. Poly-Si thin-film transistor technology and a low temperature method to deposit an ultrathin tunneling layer using plasma-assisted oxynitridation were used to fabricate embedded poly-Si NVM devices on glass panels. A memory window from was obtained at a low operating voltage with an erasing voltage of and a programming voltage of . Moreover, an extrapolation of the performance of the fabricated poly-Si NVM device suggests that it retains a threshold voltage window of more than 80% between the programming and erasing states up to . The results demonstrate that the proposed devices with poly-Si layers using solid-phase crystallization and ONOn stack structures have suitable switching and retention characteristics for data storage applicable to real flat-panel display applications.

Effects of gate insulator using high pressure annealing on the characteristics of solid phase crystallized polycrystalline silicon thin-film transistors

The oxidizing ambient was built using high pressure H2O vapor at 550 °C. For the solid phase crystallization (SPC) polycrystalline silicon (poly-Si) that is annealed for 1 h at 2 MPa, the oxide thickness is about 150 Å. The oxide layer is approximately 90 Å above the original surface of the poly-Si and 60 Å below the original surface. The oxide layer is used as the first gate insulator layer of thin-film transistors (TFTs). The heating at 550 °C with 2 MPa H2O vapor increased the carrier mobility from 17.6 cm2/V s of the conventional SPC process to 30.4 cm2/V s, and it reduced the absolute value of the threshold voltage (Vth) from 4.13 to 3.62 V. The subthreshold swing also decreased from 0.72 to 0.60 V/decade. This improvement is attributed mainly to the reduction in defect density at the oxide/poly-Si interface and in the poly-Si film by the high pressure annealing (HPA) process. Since the realization of excellent performance at the oxide/poly-Si interface and in poly-Si depends on the defect density, the poly-Si having the thermal oxide formed by a combined process of SPC and HPA may be well suited for fabrication of poly-Si TFTs for flat panel displays such as active matrix organic light emitting diodes.

High-Performance Solid-Phase Crystallized Polycrystalline Silicon Thin-Film Transistors with Floating-Channel Structure

High-performance solid-phase crystallized polycrystalline silicon thin-film transistors with a floating-channel active region (FC poly-Si TFTs) are proposed in this study. A high-quality poly-Si channel film accompanied by a larger grain size and fewer microstructural defects could be obtained. Compared with the conventional poly-Si TFTs (CN poly-Si TFTs), the fabricated FC poly-Si TFTs exhibit superior electrical characteristics, including lower threshold voltage, higher field-effect mobility, and lower trap state density. These electrical performance improvements could be attributed to the fact that the α-Si film with a floating-channel structure can relieve the stress generated from the crystallization process accompanying the trap state density reduction and grain size enhancement. In addition, the FC poly-Si TFTs also exhibit improved hot-carrier stress immunity due to the reduced weak Si–H bonds from fewer grain boundaries in the poly-Si channel. Therefore, the proposed FC poly-Si TFTs can be easily fabricated by conventional solid-phase crystallization, and suitable for future high-performance flat-panel display applications.

Electrical properties of solid-phase crystallized polycrystalline silicon films

Analyses of free-carrier optical absorption and Hall-effect current measurements indicated in high carrier mobilities of 32 cm2/Vs and 30 cm2/Vs, respectively, and low carrier densities of 5.0×1019 cm-3 and 3.8×1019 cm-3, respectively, for 1.1×1020 cm-3-phosphorus-doped solid-phase crystallized polycrystalline silicon films fabricated at 600 °C for 48 h. The silicon films had good crystalline properties of the crystalline grains and a low crystalline volume fraction of 0.43. A XeCl excimer laser anneal at 500 mJ/cm2 effectively increased the carrier density to 1.1×1020 cm-3, and also increased the crystalline volume fraction to 0.93. Moreover, H2O-vapor heat treatment at 1.3×106 Pa for 3 h at 260 °C reduced the density of the defect states from 6.2×1018 cm-3 to 2.6×1018 cm-3.

Comparison Study of Metal Induced Lateral Crystallized and Solid-Phase Crystallized Polycrystalline Silicon Thin Film Transistors with Different Channel Thickness

N- and P-type polycrystalline silicon thin film transistors are fabricated with channel thickness of 30 nm and 100 nm by metal induced lateral crystallization (MILC) and conventional solid-phase crystallization (SPC) of amorphous silicon. Significant improvement is obtained for the MILC devices by ultrathin channel layer. But for SPC devices, improvement is not as significant. The possible reasons are proposed and discussed.

Electrical and structural properties of solid phase crystallized polycrystalline silicon and their correlation to single-electron effects

Single-electron transistors have been fabricated in solid phase crystallized polycrystalline silicon films deposited on SiO2 layers grown on silicon substrates. The single-electron transistors consist of lateral side-gated nanowires. A Coulomb staircase is observed at 4.2 K, which is fully modulated by the side-gate voltage. Two-period conductance oscillations are observed in nanowires fabricated on 10-nm-thick buried oxide layers, while single-period oscillations are observed in nanowires fabricated on 40-nm-thick buried oxide layers. The two-period oscillations are attributed to the formation of a charge layer in the silicon substrate. The single-electron effects are also studied as a function of the nanowire dimensions and annealing or oxidation treatments. The effects are correlated to the structure of the polysilicon film, characterized using transmission electron microscopy, Raman spectroscopy, and electron spin resonance analysis. These measurements demonstrate the significance of single-electron charging effects on electron transport in nanometer-scale complementary metal-oxide semiconductor systems.

Effects of Deposition Parameters on Crystallization of Pecvd Amorphous Silicon Films

AbstractPlasma-enhanced chemical vapor deposition was used to deposit a-Si:H thin films (∼ 1000 Å) at various temperatures below 300°C on Coming 7059 glass substrates using a silane-based plasma. These films were used as precursor materials to produce solid phase crystallized polycrystalline silicon (poly-Si) by conventional furnace annealing at 600°C in N2 ambient. The precursor a-Si and final poly-Si films were examined using spectroscopic ellipsometry and transmission electron microscopy. Precursor film deposition temperatures were found to affect the void density in the a-Si film and grain size in the resulting poly-Si film with lower deposition temperatures leading to higher void density in the a-Si film and larger grain size in the poly-Si film.