Solder Voids Research Articles

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.

Solder Void Formation in Lead Free Solder

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Micro‐via approaches for reducing solder voiding

PurposeThe purpose of this paper is to evaluate the influence of microvia design on solder joint reliability and to present a printed circuit board (PCB) microvia design approach capable of reducing or eliminating voiding in solder joints.Design/methodology/approachFive different types of via‐in‐pad designs were incorporated into a test vehicle and their performance evaluated using a variety of standard reliability tests.FindingsSolid vias, composed of 99.5 percent pure copper can be used to eliminate voiding in solder joints. Such vias are also much more robust than those employing metallic paste or other filled materials. Solid vias with flat surfaces have been shown to be able to meet the requirements of common reliability test standards and to offer a process compatible with traditional PCB manufacturing.Research limitations/implicationsThe occurrence of voiding in solder joints has been shown to be significantly influenced by microvia design. Although a design is reported for reducing/eliminating voiding, other factors that can cause voiding should be investigated. Also, further extended accelerated reliability testing could be undertaken to determine comparative long‐term reliability.Originality/valueSerious voiding in solder joints is a major threat to the quality and reliability of electronics assemblies, mainly due to its role as a stress concentrator and particularly with the move to lead‐free assembly. Methods for reducing and eliminating the occurrence of voiding are needed by electronics assemblers and this work proposes one such method that can be implemented at the circuit board design stage.

Experimental and numerical results correlation during extreme use of power MOSFET designed for avalanche functional mode

Cost, weight and size reduction constrained designers of power electronic for micro hybrid vehicle to use power MOSFET under extreme conditions like avalanche mode. This paper shows the influence of the solder voids onto the die temperature distribution of a specifically designed power MOSFET. In the first part of this paper, a methodology is presented to perform fast dynamic temperature measurements during MOSFET avalanche (400 A–80 μs). In the second part of the paper, a comparison between experimental results and finite elements electro-thermal simulation is shown for power MOSFET operating in high conduction mode (500 A–100 ms). Finally the correlated numerical model is used to evaluate the sensitivity to solder voids of the chip temperature distribution.

Durability of Pb‐free solder between copper interconnect and silicon in photovoltaic cells

AbstractThe thermal cycling durability of large‐area Pb‐free (Sn3.5Ag) solder between silicon semiconductor and copper interconnects in photovoltaic (PV) cells is assessed and compared to benchmark results from Pb‐based (Sn36Pb2Ag) PV cells. Accelerated thermal cycling tests have been conducted on PV cells of both solder compositions, and the increase in series resistance due to interconnect damage has been characterized using in situ dark I–V measurements. Both the Pb‐free and Pb‐based cells show a steep initial rise followed by a steady rate of increase in degradation histories, with the Pb‐free cells showing a more pronounced ‘knee’ in the degradation curves. Extrapolation of the degradation data for both solders suggests that Pb‐free cells are four times more durable than the Pb‐based cells at the test condition. This superior thermal cycling fatigue durability of Pb‐free cells was also confirmed with physics of failure (PoF) analysis, consisting of nonlinear finite element (FE) stress analysis and an energy‐partitioning (E‐P) solder fatigue model. FE models error‐seeded with manufacturing voids in the solder interconnect predicted a significant reduction in the thermal cycling durability with increasing solder void density. However, even the most voided Pb‐free cells modeled are predicted to be twice as durable as void‐free Pb‐based cells, under the accelerated temperature cycle used in the test. The acceleration factor (AF) predicted by the PoF analysis for a typical service environment is three times higher for Pb‐free cells than that for Pb‐based cells. Copyright © 2010 John Wiley & Sons, Ltd.

Improvements in Solid State Lighting Applications with the use of Traditional Thick Film Technology.

As the LED market continues to grow and overtake many other lighting technologies such as incandescent and compact fluorescent bulbs (CFL), there are many challenges that LED manufacturers face. As demand for higher power and longer life continue to drive LED adoption in lighting applications, manufacturers must be able to find ways to increase thermal efficiency while reducing cost for LED package designs. In this paper, the benefits of a new Pb Free smooth-print thick film Ag conductor are examined in comparison to more traditional die attach methods, which include plated thin films, and polymer based die attach adhesives. A smooth print thick film conductor can offer the best of both worlds as cost and process simplicity are comparable to a polymer system, while thermal efficiency and solderability are comparable to plated thin film systems. As surface smoothness increases, there is also the benefit of reduced solder voiding and material usage; solder voiding is a major contributor to thermal inefficiency. In the case of high cost solders such as Au/Sn, the reduction in material usage can translate to significant cost savings. Thermal efficiency, solderability, and manufacturing complexity must all be considered as new LED package designs are sought that reduce overall cost while increasing thermal efficiency and effective operational life. This paper evaluates these benefits as they apply to wire bonding, thermal dissipation, surface smoothness, and voiding at the die-package interface. Each of these properties can affect thermal efficiency of the package, which in turn affects the light output and effective operational life of the LED. A new option for LED package design is presented, and this packaging can allow for cost-effective manufacturing while keeping up with industry demands of higher power, maximum efficiency, and greater effective operational life.

Drop Test Simulation for the Component-Level Reliability of Module Packages

The component-level drop reliability of micro-electronic packages has been a concern. Proper modeling approaches can significantly reduce the time and costs and provide valued data support not only on the failure analysis but also on product development. Based on finite element methods, the presented study performed explicit dynamic drop modeling to simulate the actual drop tests using ANSYS and LS-DYNA. A generic over-molded LGA (land grid array) module was selected and 3D parametric models were utilized to carry out the study. As in the actual drop test, the standard JEDEC test board and JEDEC drop condition were applied. The over-molded modules together with the test board under 1500G gravity was simulated to identify the failure locations. The results were fairly correlated to the actual FA observation. Potential key factors such as solder pad size, pitch size, module size, and thickness were studied through the parametric modeling. The impact of board side defect, such as solder void, was also studied because it is common to have this kind of defect in assembly. Besides component-level drop reliability, we also studied the board-level drop reliability by investigating the LGA solder stress.

An Assessment of Immersion Silver Surface Finish for Lead-Free Electronics

The worldwide transition to lead-free electronics has increased the usage of several lead-free pad finishes for electronic assembly manufacturers, including immersion silver, immersion tin, electroless nickel-immersion gold, and organic solderability preservatives. This study assesses and compares immersion silver as a circuit board finish in terms of its ease of use, wettability, solderability, shelf life, appearance, solder joint strength, intermetallic and void formation, reliability, and costs.

Void nucleation by vacancy condensation

AbstractA computational simulation of Kirkendall voiding in metallic materials is presented. After a brief explanation of the phenomena and its consequences on the reliability of microelectronic components we introduce a constitutive model for void nucleation and growth which is based on vacancy diffusion and rate–dependent inelastic deformation. This model can be used to predict the temporal development of voids in solder during thermal cycling and/or impact loading. A numerical study illustrates the potential of the model for the failure analysis. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Consideration of temperature and current stress testing on flip chip solder interconnects

This work discusses the experimental set-up and data interpretation for high temperature and current stress tests of flip chip solder joints using the four-point Kelvin measurement technique. The single solder joint resistance responses are measured at four different four-point Kelvin structure locations in a flip chip package. Various temperatures (i.e., 125–165 °C) and electric current (i.e., 0.6–1.0 A) test conditions are applied to investigate the solder joint resistance degradation behavior and its failure processes. Failure criterion of 20% and 50% joint resistance increases, corresponding to solder and interfacial voiding, are employed to evaluate the solder joint electromigration reliability. The absolute resistance value is substantially affected by the geometrical layout of the metal lines in the four-point Kelvin structure, and this is confirmed by finite element simulation. Different current flow directions and strengths yielded different joint resistance responses. The anode joint, where electrons flow from the die to the substrate, usually measured an earlier resistance increase than the cathode joint, where electrons flow in the opposite direction. The change in measured joint resistances can be related to solder and interfacial voiding in the solder joint except for ±1 A current load, where resistance drop mainly attributed to the broken substrate Cu metallization as a result of “hot-spot” phenomenon. The solder joint temperature increases above the oven ambient temperature by ∼25 °C, ∼40 °C and ∼65 °C for 0.6 A, 0.8 A and 1.0 A stress current, respectively. It is found that two-parameter log-normal distribution gives a better lifetime data fitting than the two-parameter Weibull distribution. Regardless of failure criterion used, the anode joint test cells usually calculated a shorter solder joint mean life with a lower standard variation of 0.3–0.6, as compared to the cathode joint test cells with a higher standard variation of 0.8–1.2. For a typical flip chip solder joint construction, electromigration reliability is mainly determined by the under bump metallization consumption and dissolution, with intermetallic compound formation near the die side of an anode joint.

Effect of Selected Process Parameters on Durability and Defects in Surface-Mount Assemblies for Portable Electronics

This paper presents a systematic approach to study the effect of manufacturing variables on the creation of defects and the effect of those defects on the durability of lead-free (Pb-free) solder joints. An experiment was designed to systematically vary the printing and reflow process variables in order to fabricate error-seeded test assemblies. The error-seeded samples were then inspected visually and with X-ray, to identify different types of defects, especially voids, and then test for electrical performance. The specimens were subjected to an accelerated thermal cycling test to characterize the durability of these error-seeded specimens and to study the effect of each manufacturing variable on the durability of the solder joints. The response variables for the design of experiments are thermal cycling durability of the solder joints and void area percentage in ball grid array (BGA) solder joints. Pretest microstructural analysis showed that specimens produced under inadequate reflow profiles suffered from insufficient wetting and insufficient intermetallic formation. Statistical analysis of the response variables shows that waiting time, heating ramp, peak temperature, and cooling rate have nonlinear effects on thermal cycling durability. Two variables in particular [peak temperature and waiting time (the time waited after the solder paste barrel was opened and before print)] appear to have optimum values within the ranges investigated. Statistical analysis of void percentage area for all design of experiment (DOE) runs show that higher stencil thickness results in higher void percentage and that void percentage increases as time above melt and peak temperature increases.

Die Bonding Issues on Silicon Carbide Diodes

We report on the die bonding processes and how the surface roughness and metallization schemes affect the processes of die bonding in 4H-SiC device fabrication using a soldering test and die shear test (DST) with differently prepared 4H-SiC samples. The first set of samples (FZ#1 and FZ#2) was capped with sequentially evaporated Ti and Au on an annealed Ni layer. The second set of samples (FZ#3 and FZ#4) and the third set of samples (FZ#5 and FZ#6) were prepared by 4μm-thick Au electroplating on an annealed Ni layer and an un-annealed Ni layer, respectively. The quality of the soldering, such as the solder coverage, void, and adhesion, was characterized by optical microscope, X-ray microprobe, and DST. We found that the samples (FZ#4 and FZ#6) deposited by Au electroplating on C-face (bottom-side) 4H-SiC provided a satisfactory result for the tests of solder coverage, void, and DST and also realized the cleaning process prior to the electroplating and soldering was the most crucial in the die packaging processes of vertical structure devices. The void fraction measured by X-ray microprobe for the samples, FZ#4 and FZ#6 was 2.2% (average for 5 samples) and 0.8% (average for 3 samples), respectively.

Effects of pre-bump probing and bumping processes on eutectic solder bump electromigration

This paper investigates the electromigration reliability of flip chip packages with and without pre-bump wafer probing via high temperature operation life test (HTOL) using printed and electroplated bumps. Under bump metallization (UBM) of printed and electroplated bumps is a thin film of Al/Ni(V)/Cu and Ti/Cu/Ni, respectively, while the bump material consists of eutectic Sn/Pb solder. Current densities from 7380 to 20 100 A/cm 2 and ambient temperatures at 100, 125 and 150 °C are applied in order to study their impact on electromigration. The results reveal that the bump temperature has a higher influence than the current density when it comes to bump failures. The observed interconnect damage is from bumps with electrical current flowing upward into the UBM/bump interface (cathode). Identified failure sites and modes reveal structural damage at the region of the UBM and UBM/bump interface, in the form of solder voiding and cracking. The effects of current polarity, current crowding, and operation temperature are key factors to electromigration failures of flip chip packaging. The maximum allowable current density of the electroplated bumps is superior to the printed bumps by a factor of 3.0–3.7 times. Besides, the median time to failure (MTTF) of without-underfill packaging is preferred to that of with-underfill packaging by 1.5–2.2 times. Furthermore, the differences in MTTF between pre-bump and without pre-bump probing procedures are 2.0–19.4% and 1.6–10.3% for printed and electroplated bumps, respectively.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

Extraction of bonding strain data in diode lasers from polarization-resolved photoluminescence measurements

A technique to determine strain in diode lasers by matching measured polarization-resolved photoluminescence to a finite element method model is described. The code is shown to be able to fit well a finite element model with degree of polarization measurements to extract strain information from diode lasers and predict strain values owing to die bonding. It is useful in characterizing die bonding processes and in detecting solder voids which can impact the reliability of devices. Using the code, it is demonstrated that there are differences in the die bonding strain from different die attachments. The bonding strain from InP chips die bonded to copper and silicon chip carriers using gold–tin solder are examined.

Characterization of solder interfaces using laser flash metrology

Thermal conductivity and normalized thermal resistance measurements on eight bulk solders and three tri-layer samples were performed using the laser flash technique. In this study, the laser flash technique is demonstrated to be capable of measuring thermal conductivity of 0.7-mm-thick solders ranged from 20 to 90 W/mK with an average uncertainty of 11%. Laser flash was then used to measure the intrinsic thermal resistance of Cu/Solder/Cu, tri-layer sandwich structures. Analysis shows that the total intrinsic thermal resistance measurement is confounded by sample voiding. C-SAM scanning ultrasonic microscope metrology was shown to be useful in providing information regarding solder voiding and the quality of the solder/copper interfaces. The laser flash method also proved to be useful in assessing voiding effects resulting from different assembly processes and different contacting surfaces on package thermal performance.

Ethylene glycol ether free solder paste development

There are growing concerns in the electronics industry for not only finding alternatives to lead but also other potentially hazardous materials as well. This paper summarizes the development of ethylene glycol ether (EGE)-free solder flux for the formulation of lead-free solder pastes. Replacing the toxic components in the flux was only the first challenge, the criteria of commercially proven pastes also had to be met. Both commercial and in-house solder paste formulations were evaluated for printability, reflow, wetting, flux residue removal, and solder void characteristics. Two critical issues, solder bump boids and flux residue removal, were identified and associated with the high temperature reflow of Pb-free pastes. These issues were not effectively improved by the existing commercial EGE-free solder pastes. New solder paste formulations were developed utilizing alternative chemistry than those found in traditional solder paste fluxes. These pastes, some, of which are also water soluble, reduced void frequency and size by more than 4x as compared to vendors' pastes. Solder bump height uniformity of 135 4 m within each die was consistently achieved. Thermal-mechanical reliability tests were performed on various lead-free solder alloys using the new flux formulations. The reliability of flip chip assembled DCA on organic boards with both OSP/Cu and Cu/Ni/au pad metallizations were comparable to eutectic Sn63Pb37 bumped assemblies using commerical pastes.

Implementation of the pin-in-paste process in a contract manufacturing environment

The pin-in-paste process was developed and validated for a contract manufacturing PCB assembly environment. A systematic approach was used to implement this process in a production environment. The sequence used for process development included solder paste volume calculations for through hole components (THCs), stencil aperture design for the pin-in-paste application, solder paste deposition through stencil printing, reflow profile development, inspection, and testing. A series of experiments were conducted to identify the 'process window' associated with each process step. The required volume of solder paste was computed using a set of empirical equations. The stencil printing process was 'optimized' using a 'design of experiments' based approach. Response surfaces were plotted and used to identify the 'optimal' print parameters. Thermal profiles were developed for reflow soldering the THCs in conjunction with the surface mount components (SMCs) in a single reflow pass. The assemblies were built using the 'optimized' process parameters. The assemblies were then inspected under an X-ray system to check for solder voiding. Electrical testing was then done to check for solder shorts and open connections. The shape of the solder joints was similar to a wave soldered joint, voiding was minimal, and there was no instance of solder shorts or an open connection. The solder joints were then cross-sectioned as a part of destructive testing. The cross sections showed the formation of good positive fillets (both top and bottom fillet), the solder paste had filled the plated through hole (PTH) completely, and voiding was minimal.

Failure analysis of solder bumped flip chip on low-cost substrates

Failure analyses of 63/37 Sn/Pb solder bumped flip chip assemblies with underfill encapsulant are presented in this study, Emphasis is placed on solder flowed-out, nonuniform underfill and voids, and delaminations. The X-ray, scanning acoustic microscope (SAM), and tomographic acoustic micro imaging (TAMI) techniques are used to analyze the failed samples. Also, cross sections are examined for a better understanding of the failure mechanisms. Furthermore, temperature dependent nonlinear finite element analyses together with fracture mechanics are used to determine the effects of underfill void sizes on the flip chip solder joint reliability.

Examination of Various Soldered Surfaces and Electronic Components by Confocal Microscopy

The unique advantages of confocal microscopy are used to explore four cases of interest: (i) voids in solder (depth and surface texture determined), (ii) steam vs ambient aged solder coupons (significant differences detected), (iii) integrated circuit construction (sub‐surface contamination by µm‐size particles observed) and (iv) circuit boards and solder pads (non‐destructive optical sectioning through no‐wash flux layers). It is shown that confocal microscopy strongly complements SEM (scanning electron microscopy); SEM alone presents an incomplete description of a solder surface and in fact can sometimes produce misleading results.