Drop Test Simulation for the Component-Level Reliability of Module Packages

Abstract

The component-level drop reliability of micro-electronic packages has been a concern. Proper modeling approaches can significantly reduce the time and costs and provide valued data support not only on the failure analysis but also on product development. Based on finite element methods, the presented study performed explicit dynamic drop modeling to simulate the actual drop tests using ANSYS and LS-DYNA. A generic over-molded LGA (land grid array) module was selected and 3D parametric models were utilized to carry out the study. As in the actual drop test, the standard JEDEC test board and JEDEC drop condition were applied. The over-molded modules together with the test board under 1500G gravity was simulated to identify the failure locations. The results were fairly correlated to the actual FA observation. Potential key factors such as solder pad size, pitch size, module size, and thickness were studied through the parametric modeling. The impact of board side defect, such as solder void, was also studied because it is common to have this kind of defect in assembly. Besides component-level drop reliability, we also studied the board-level drop reliability by investigating the LGA solder stress.