SOI Substrate Research Articles

Photon-Trapping Microstructure for InGaAs/Si Avalanche Photodiodes Operating at 1.31 μm.

With the rapid development of photo-communication technologies, avalanche photodiode (APD) will play an increasingly important role in the future due to its high quantum efficiency, low power consumption, and small size. The monolithic integration of optical components and signal processing electronics on silicon substrate chips is crucial to driving cost reduction and performance improvement; thus, the technical research on InGaAs/Si APD is of great significance. This work is the first to demonstrate the use of a photon-trapping (PT) structure to improve the performance of the InGaAs/Si APD based on an SOI substrate, which exhibits very high absorption efficiency at 1310 nm wavelength while the thickness of the absorption layer is kept at 800 nm. Based on the optical and electrical simulations, an optimized InGaAs/Si PT-APD is proposed, which exhibits a better performance and a higher responsivity compared to the original InGaAs/Si APD.

The advantages of co-digestion of vegetable oil industry by-products and sewage sludge: Biogas production potential, kinetic analysis and digestate valorisation.

The production of edible vegetable oils generates considerable amounts of energy-rich waste, which is usually not utilised fully. Besides, inefficient management of such wastes can have a negative impact on the environment. On the other hand, this waste can also serve as a raw material for the production of high value-added products, such is biogas. The mono-digestion of seven different by-products and wastes from the vegetable oil industry was investigated in this study: Pumpkin seeds press cake (PSPC), grape seeds press cake (GSPC), olive mill pomace (OMP), coconut oil cake (CC), filtration additive (FA), spent bleaching earth (SBE) and sludge from a vegetable oil industry (SOI) wastewater treatment plant. In addition, co-digestion of these substrates was performed with municipal sewage sludge (SS). Besides inoculum, rumen fluid was added to the reactors to enhance biogas production. The biogas production potential of the tested substrates was monitored by measuring various parameters. A kinetic analysis was later carried out and a growth test was performed on the digestates to evaluate their potential for agricultural use. The highest biogas yields in the mono-digestion test were obtained with the substrates with the highest fat content: 1402, 1288, 830 and 750mL of biogas/gVS for SOI, FA, PSPC and CC substrate, respectively. Co-digestion of SS with by-products of vegetable oil industry such as FA, SBE, CC, SOI and PSPC increased the biogas yields by 94.9%, 74.1%, 30.8%, 27.4% and 23.6% compared to SS mono-digestion. Furthermore, the data for mono-digestion of PSPC, GSPC, and FA, and co-digestion of SS with these substrates, CC and SBE, have not been found in the literature to date. The maximum methane content ranged from 61 to 74vol%, while the chemical oxygen demand removal efficiency ranged from 42 to 78%. Relatively high fatty acids contents and ammonium concentrations were measured in the reactors. Kinetic analysis showed the best fit to the experimental data for the Cone kinetic model (R2>0.98). The First order kinetic model, Monod, and the modified Gompertz model also exhibited high R2 values. The digestates obtained from co-digestion proved to be excellent in the cress seeds growth test at digestate concentrations of 5-10wt%, while higher concentrations had a toxic effect.

An A0 mode Lamb-wave AlN resonator on SOI substrate with vertically arranged double-electrodes

In this paper, a novel vertically arranged double-electrodes A0 mode Lamb-wave AlN resonator on SOI substrate with a high electromechanical coupling coefficient and high figure of merit (FOM) is reported. The AlN resonator has a sandwich structure with aluminum and N-type doped silicon as electrode layers and a 500 nm thick AlN film as piezoelectric layer. The resonator has only two electrodes vertically arranged rather than horizontal interdigitated (IDT) electrodes which is common in conventional Lamb-wave resonators. The electrode gaps for the vertically arranged double-electrodes resonators are defined by AlN layer thickness rather than by photolithography for lateral field excitation resonators, which results in higher electric field strength and higher electromechanical coupling efficient (). Compared with conventional thickness field excitation (TFE) resonators with floating bottom electrodes, the vertically arranged double-electrodes resonators have higher electric field strength as the potential difference is larger between the top electrode and bottom electrode than that between the IDT electrodes and floating electrode. As a result, a higher electromechanical coupling coefficient is achieved. Furthermore, the resonant frequency of the vertically arranged double-electrodes resonator presented in this work can be defined by photolithography by controlling the width of the silicon layer. The of the vertically arranged double-electrodes resonator calculated from the measurement results of admittance versus frequency by numerically fitting with the Butterworth Van Dyke model shows an increase by 3.85 times, from 0.073% to 0.281% compared with conventional TFE resonators, and the FOM also increases by three times, from 2.66 to 7.99. This work provides a new structure to design future AlN Lamb-wave resonators on SOI substrate.

(Invited, Digital Presentation) Approach to Neuromorphic Computing with Ferroelectric Schottky Barrier FETs

Neuromorphic computing inspired by neural network systems of the human brain enables energy efficient computing as a solution of the von Neumann bottleneck. A neural network consists of thousands or even millions of neurons which communicate with each other through connected synapses. Synapses can memorize and process the information simultaneously. The plasticity of a synapse to strengthen or weaken its activity over time make it be capable of learning and computing. Thus, artificial synapses which can emulate functionalities and the plasticity of bio-synapses form the backbone of a neuromorphic computing system.Non-volatile memories with two-terminals, like resistive random-access memory (ReRAM), phase change memory (PCM), are attractive candidates for artificial synapses. However, signal processing and learning cannot be performed simultaneously in these two-terminal synapses. FeFET, similar to a MOSFET structure using CMOS compatible HfO2 based ferroelectrics as gate oxide forms three-terminal synapses offering high endurance, good performance and high energy efficiency. In contrast to two-terminal devices, three terminal FeFET based synapses can perform processing and learning at the same time. In order to maintain the ferroelectric properties of an HfO2 based ferroelectric film, high temperature annealing should be avoided after the ferroelectric layer deposition. In this paper, we present ferroelectric NiSi2 source/drain Schottky barrier (SB) MOSFET (FE-SBFET) structure (Fig.1a), which requires neither ion implantation nor thermal activation of source/drain contacts at high temperatures.FE-SBFETs were fabricated on SOI substrates with a boron-doped (1016 B/cm-3), 55 nm thick top Si layer and a 145 nm thick buried oxide (BOX) layer. Very thin (9 nm) single crystalline NiSi2 layers which offer superior properties of uniform and stable SB contacts on Si are used at source/drain regions. A gate stack consisting of 10 nm thick Hf0.5Zr0.5O2 (HZO) layer and a 40 nm thick TiN layer are deposited by ALD and sputtering, respectively. A rapid thermal annealing at 500 °C is performed to crystallize the HZO into a ferroelectric phase before the gate patterning. The fabricated device has a channel length of 10 µm and a gate width of 10 µm. The overlap between the top gate and NiSi2 is 6 µm along the channel and 10 µm wide on each side. The ferroelectric polarization modulates both the SB at the source/drain contacts as well as the potential in the channel, thus changing the carrier injection through the SB. The Id-Vg transfer characteristics of a p-type FE-SBFET shows a clockwise hysteresis which is caused by the ferroelectric polarization switch.The excitatory post-synaptic current (EPSC), one of the typical short-term synaptic plasticity features for biologic synapses, is characterized by measuring the transient drain currents for a voltage pulse on the gate of a FE-SBFET (Fig.1b). The amplitude of the pulse VAM changes from -0.2 to -1.2 V with a fixed pulse width tpw=1 μs. We found that the EPSC peak value increases linearly with VAM. It shows a very low energy/spike consumption of 2fJ/spike at VAM=-0.2 V, demonstrating a very high energy efficiency. From the EPSC measurements with repeated gate voltage pulses paired-pulse facilitation/depression (PPF/PPD) are characterized showing an exponential decay, similar to biological synapses.The long-term synaptic plasticity of FE-SBFET synapses is characterized by a series repeated identical or non-identical pulses. The later can improve the long-term potentiation/depression (LTP/LTD) symmetry and linearity. The measurements show a large Gmax/Gmin ratio, very high endurance and small cycle-to-cycle (CTC) variation (1.06%) due to the perfect contact of NiSi2 (Fig.1c). The biological neuron-like spike-timing-dependent plasticity (STDP) is characterized for the FE-SBFET synapse. The results show an asymmetric anti-Hebbian STDP, which is one of the biological STDP functionalities (Fig.1d).In conclusion, the fabricated FE-SBFET synapse exhibits multiple synaptic functions with high endurance and small variations. The ultra-low energy/spike consumption indicates a high potential for low power neuromorphic computing applications. Acknowledgement: This work was supported by the Federal Ministry of Education and Research (BMBF, Germany) in the project NEUROTEC (16ME0398K). Figure 1

(Digital Presentation) Diffusion and Segregation in Highly Stacked Ge0.9Sn0.1/Ge:B and Ge0.95Si0.05/Ge:P Epilayers

GeSn and GeSi are promising channel materials for gate-all-around (GAA) devices to achieve the high ION thanks to the high mobility [1, 2]. The undoped channels are used to reduce the impurity scattering and to further enhance the mobility. The GAA structure with high number of stacked channels can further enhance the ION for a fixed footprint. The dopant diffusion and segregation play an important role on GAA device structure design. In this work, the dopant diffusion and segregation effects of B and P in highly stacked Ge0.9Sn0.1 and Ge0.95Si0.05 epilayers are investigated, respectively.The Ge:B/Ge0.9Sn0.1/Ge:B epilayers were grown on the Ge-buffered SOI substrate at 320°C and 100 torr by chemical vapor deposition (CVD) using SnCl4, Ge2H6, and B2H6 precursors. The 160nm undoped Ge buffer was grown with an 800℃ annealing to confine the misfit dislocations at Ge/Si interface. For the 8 stacked Ge0.9Sn0.1 epilayers, 36 nm Ge0.9Sn0.1 layers sandwiched by 24 nm Ge:B layers were grown. Transmission electron microscopy (TEM) image of Ge:B/Ge0.9Sn0.1/Ge:B epilayers is shown in Fig. 1(a). The Ge:P/Ge0.95Si0.05/Ge:P epilayers were grown on the Ge-buffered SOI substrate at 350°C and 100 torr by SiH4, GeH4, and PH3 precursors using similar Ge buffer layers. For the 8 stacked Ge0.95Si0.05 epilayers, 24 nm Ge0.95Si0.05 layers sandwiched by 25 nm Ge:P layers were grown. TEM image of Ge:P/Ge0.95Si0.05/Ge:P epilayers is shown in Fig. 1(b). Note that both Ge0.9Sn0.1 and Ge0.95Si0.05 channel layers are unintentionally doped. In the 8 stacked Ge0.9Sn0.1 epilayers, the [B] in the Ge:B layers is as high as ~2.0 ×1021 cm−3 (Fig. 2(a)). In the 8 stacked Ge0.95Si0.05 epilayers, the [P] in the Ge:P layers is as high as ~2.2 × 1020 cm−3 , and the minimum [P] in the Ge0.95Si0.05 channel layers is from ~4.2 ×1017 cm−3 to ~1.5 ×1018 cm−3 (Fig. 2(b)).The B and P diffusion phenomena in the GeSn and GeSi layers are investigated, respectively. The deep undoped GeSi layers have higher [P] due to higher thermal budget (Fig. 3). Note that the P atoms diffuse from the Ge:P layers into GeSi channels during the epitaxial growth. The similar [B] ~3x1016cm-3 in the 2nd to 8th GeSn layers is due to the B detection limit of SIMS analysis (Fig. 3). Note that the decay length (nm/decade) is defined in Fig. 4 and Fig. 5. The decay length of [B] on the top side (4.3 nm/decade) is larger than that on the bottom side (2.9 nm/decade) due to SIMS knock-on effect [3] (Fig. 4). On the other hand, the P segregation [4] increases the decay length on the bottom side of GeSi layers (Fig. 5). Both the decay length of [B] and [P] increase with the increasing depth (Fig. 6) due to the higher thermal budget of the deeper layers in the CVD chamber. In addition, the difference of [B] decay length between top and bottom sides increases with the increasing depth of epilayers (Fig. 6). For the Ge:P/GeSi/Ge:P epilayers, the difference between top and bottom [P] decay length (less than 0.9 nm/decade) is smaller than that of [B] decay length in Ge:B/GeSn/Ge:B epilayers (larger than 1.4 nm/decade) due to P segregation, and the difference decreases for deep layers.AcknowledgmentThis work is supported by the Ministry of Science and Technology, Taiwan (MOST 110-2622-8-002-014-, 110-2218-E-002-030-, and 110-2218-E-002-042-MBK) and the Ministry of Education, Taiwan (NTU-CC-110L892601). The support by Taiwan Semiconductor Research Institute (TSRI), Hsinchu, Taiwan, is also highly appreciated.

Graphene/SOI-based self-powered Schottky barrier photodiode array

We have fabricated a four-element graphene/silicon on insulator (SOI) based Schottky barrier photodiode array (PDA) and investigated its optoelectronic device performance. In our device design, monolayer graphene is utilized as a common electrode on a lithographically defined linear array of n-type Si channels on a SOI substrate. As revealed by wavelength resolved photocurrent spectroscopy measurements, each element in the PDA structure exhibited a maximum spectral responsivity of around 0.1 A/W under a self-powered operational mode. Time-dependent photocurrent spectroscopy measurements showed excellent photocurrent reversibility of the device with ∼1.36 and ∼1.27 μs rise time and fall time, respectively. Each element in the array displayed an average specific detectivity of around 1.3 × 1012 Jones and a substantially small noise equivalent power of ∼0.14 pW/Hz−1/2. The study presented here is expected to offer exciting opportunities in terms of high value-added graphene/Si based PDA device applications such as multi-wavelength light measurement, level metering, high-speed photometry, and position/motion detection.

Effect of SOI substrate on silicon nitride resistance switching using MIS structure

Several resistive memory technologies (RRAMs) are prominent, but few are fulfilling the requirements for CMOS integration and meet the commercialization standards. In this work, the fabrication and electrical characterization of a fully compatible CMOS process on SOI substrate of 1R silicon SiN-based resistance switching (RS) MIS devices is presented. The RS characteristics are compared with the same devices previously fabricated on bulk silicon.

Localized Backside Etching Structure of SOI Substrates on Total Ionizing Dose Effect Hardening for RF Applications

In this work, the localized backside etching (LBE) structure is introduced as a strategy for total ionizing dose (TID) irradiation hardening. Immunity to TID-irradiation-induced radio frequency (RF) property degradation is observed for the first time in SOI substrates with the LBE structure. Identical co-planar waveguide transmission lines (CPW TLines), crosstalk characterization structures, and planar spiral inductors are designed and fabricated on different 8-in SOI wafers to characterize the RF properties of substrates. Electrical characterization in the frequency ranges from 100 MHz to 40 GHz reveals that the LBE structure is beneficial to suppressing the parasitic surface conduction (PSC) effect, which will lead to better RF properties of SOI substrate. It is shown that under <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> Co <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> -ray irradiation, RF losses are significantly increased in the case of conventional substrates. In contrast, LBE substrates are almost insensitive to TID irradiation due to suppression of PSC. A developed physical model is proposed to characterize the behavior of inductors under PSC and TID effects, and the improvement by LBE structure on RF TID tolerance is separated through model parameter extraction.

Silicon on isolator ribbon field-effect nanotransistors for high-sensitivity low-power biosensor

Silicon nanowire field-effect transistors are discussed as biological sensors due to their excellent sensitivity due to the large surface-to-volume ratio and high selectivity with respect to a large number of analytes. A miniature sensor based on a long-channel fin field-effect transistor as a surface charge detector is being investigated. The three-gate configuration offers undeniable advantages over planar devices, since the edges are about a hundred nanometers wide and are characterized by increased conductivity, which leads to higher sensitivity. The characteristics of the transistor are optimized using 3D modeling performed by the computer-aided design software package TCAD, depending on the topological parameters of the transistor and the level of control voltages. Based on the obtained simulation results, a chip was manufactured on a SOI substrate based on self-aligning CMOS-compatible technological processes from top to bottom. It is established that thin structures with a reduced level of doping and low supply power have promising electrical characteristics for an effective approach to scaling a high-resolution pH sensor, which is of particular interest to integrated pH bioanalytics based on CMOS technology.

High-Q photonic crystal cavities for nanolasers on patterned silicon-on-insulator substrates

As the performance of the silicon-based nanolaser is developing, further miniaturization of laser size is expected, and nanocavities will make it possible to avoid defects contained in the gain cavity. Hence, the miniaturization of the cavity is becoming necessary. In this letter, a photonic crystal cavity for the nanolaser grown on the patterned SOI substrate was proposed and analyzed in detail. The quality (Q) factor of 5 × 105 at a resonant wavelength of 1.516μm was demonstrated. And an insight into the variation of the resonant wavelength and the dependence of the Q-factor on the geometrical parameters of the laser cavity was obtained through simulation. For current injection, a pillar under the cavity region was introduced, the Q-factor over 104 was obtained as the length of the pillar was less than 160 nm. The effects of fabrication errors on the performance of cavities were also discussed by simulation.

Self-Aligned Transparent-Gate ITO/Germanium Nanospheres/SiO2/SiGe-Nanosheets photoMOSFETs on Silicon Nitride Platform

We report experimental fabrication and characterization of photoMOSFETs with self-aligned gate-stacking heterostructures of indium-tin-oxide (ITO)/Ge nanospheres/SiO₂-shell/Si_1-xGe_x-nanosheets. Array of Ge-nanosphere/SiO₂-shell/SiGe-nanosheet heterostructures was created in a self-organized, CMOS approach using the thermal oxidation of lithographically-patterned poly-Si_0.85Ge_0.15 nanopillars over buffer layers of Si₃N₄ on top of SOI substrates. With a polysilicon dummy-gate, source and drain self-align with the transparent ITO gate using a replacement-metal-gate process. Very high photocurrent gain, large photoresponsivity, as well as improved input capacitance and 3dB frequency were experimentally achievable in our photoMOSFETs. The pivotal roles of Ge-optical gate and SiGe-channel for large photoresponsivity and current gains were analyzed via numerical simulation.

Low cost, contamination-free, and damage-free fabrication of PZT MEMS on SOI substrate

This paper reports a generalised process flow for the fabrication of lead zirconate titanate based piezoelectric micro electromechanical system devices. The optimised process can be used to realise several devices with different 1D and 2D geometries on a single wafer. All the state-of-the-art fabrication methods introduce some damage to the active piezoelectric material. This damage entails the need for an additional step of recovery anneal in the fabrication process. Our process was designed and optimised to avoid any such damage to the Lead Zirconate Titanate (PZT) layer. Remnant polarisation and effective transverse piezoelectric coefficient (e 31, f ) were used as metrics to quantify the damage to the PZT layer. It is shown that our process does not damage the PZT thin film during the fabrication, and hence no recovery anneal is required. We observe a ∼3× improvement in remnant polarisation and ∼2× improvement in e 31, f of PZT thin film compared to the PZT thin film subjected to our previous fabrication process. Moreover, the process explained here uses only wet chemical methods for patterning of contaminating agents (PZT and platinum), making it a cost-effective process.

Photoelectric Characterization of Intended Source UTBB 1 T FDSOI Based Image Sensor

This paper presents the photoelectrical performance evaluation of proposed intended sourceUltra Thin Body Bias (UTBB) 1 T-FDSOI based image sensor and also a comparative analysis has done with conventional 1 T-UTBB based image sensor [1]. The photoelectrical conversion in proposed image sensor is achieved by utilizing back biasing in intended source UTBBFDSOI based MOSFET. Inthe proposedintended source Ultra Thin Body Bias (UTBB) 1 T-FDSOI based image sensor,the photoelectrical conversion is done within the substrate region (well region) and that signal is read out by MOSFET placed on SOI substrate. The comparative analysis between proposed image sensor and conventional 1 T-UTBB based image sensor has performed on the basis of various parameters such as back-bias voltage, thickness of buried oxide (BOX) layer and doping concentration. In this investigation the proposed image sensor has found better light sensitivity in contrast with conventional image sensor. The performance evaluation of proposed image sensor has done by TCAD simulations.

Enhanced absorption and EQE of Si MSM photodiodes with integrated periodic arrays of holes

In order to enhance the absorption of thin Si film, cylindrical-shaped holes arranged in square and hexagonal lattices with different designs of hole diameter, depth and period are integrated in the surface of Si films with a thickness of 1.5 μm and 2.5 μm on either bulk Si or SOI substrate. At the wavelengths between 800 ~ 950 nm, light bending and absorption enhancement of Si film with integrated hole array is analyzed by FDTD simulation. Hole array with a period similar to the wavelength and a diameter/period ratio around 0.7 enables a higher absorption of Si film. Si film with cylindrical-shaped holes in hexagonal lattice with a Si thickness of 1.5 μm and a hole depth of 250 nm provides an absorption of 43.16 % at 850 nm wavelength on a SiO2 substrate. Nanostructured Si MSM photodiodes are fabricated by integrating periodic arrays of holes in 1.5 μm thin absorption regions between metal fingers. The EQE is enhanced to 61 % at 850 nm, while the photodiodes without holes show only 23 %.

Clinic-on-a-Needle Array toward Future Minimally Invasive Wearable Artificial Pancreas Applications.

In order to reduce medical facility overload due to the rise of the elderly population, modern lifestyle diseases, or pandemics, the medical industry is currently developing point-of-care and home medical device systems. Diabetes is an incurable and lifetime disease, accountable for a significant mortality and socio-economic public health burden. Thus, tight glucose control in diabetic patients, which can prevent the onset of its late complications, is of enormous importance. Despite recent advances, the current best achievable management of glucose control is still inadequate, due to several key limitations in the system components, mainly related to the reliability of sensing components, both temporally and chemically, and the integration of sensing and delivery components in a single wearable platform, which is yet to be achieved. Thus, advanced closed-loop artificial pancreas systems able to modulate insulin delivery according to the measured sensor glucose levels, independently of patient supervision, represent a key requirement of development efforts. Here, we demonstrate a minimally invasive, transdermal, multiplex, and versatile continuous metabolites monitoring system in the subcutaneous interstitial fluid space based on a chemically modified SiNW-FET nanosensor array on microneedle elements. Using this technology, ISF-borne metabolites require no extraction and are measured directly and continuously by the nanosensors. Due to their chemical sensing mechanism, the nanosensor response is only influenced by the specific metabolite of interest, and no response is observed in the presence of potential exogenous and endogenous interferents known to seriously affect the response of current electrochemical glucose detection approaches. The 2D architecture of this platform, using a single SOI substrate as a top-down multipurpose material, resulted in a standard fabricated chip with 3D functionality. After proving the ability of the system to act as a selective multimetabolites sensor, we have implemented our platform to reach our main goal for in vivo continuous glucose monitoring of healthy human subjects. Furthermore, minor adjustments to the fabrication technique allow the on-chip integration of microinjection needle elements, which can ideally be used as a drug delivery system. Preliminary experiments on a mice animal model successfully demonstrated the single-chip capability to both monitor glucose levels as well as deliver insulin. By that, we hope to provide in the future a cost-effective and reliable wearable personalized clinical tool for patients and a strong tool for research, which will be able to perform direct monitoring of clinical biomarkers in the ISF as well as synchronized transdermal drug delivery by this single-chip multifunctional platform.

A simple test structure for the electrical characterization of front and back channels for advanced SOI technology development

Pseudo-MOSFET delivers a fast, simple and reliable way of characterizing electrically SOI substrates without the need of full CMOS fabrication. However, the information refers to the back interface. Here, to probe the front interface, we extend the concept to a double-gate pseudo-MOSFET. The structure provides a pertinent test vehicle for the characterization and development of transistors channel and gate stack materials in a configuration similar to fully fabricated transistors. We show that the devices with undoped terminals need specialized modeling development to describe the double gate effect. Devices with doped terminals are immediately exploitable for parameter extraction.

30 GHz GeSn photodetector on SOI substrate for 2 µm wavelength application

We report the demonstration of a normal-incidence p-i-n germanium-tin ( Ge 0.951 Sn 0.049 ) photodetector on silicon-on-insulator substrate for 2 μm wavelength application. The DC and RF characteristics of the devices have been characterized. A dark current density under − 1 V bias of approximately 125 mA/ cm 2 is achieved at room temperature, and the optical responsivity of 14 mA/W is realized for illumination wavelength of 2 μm under − 1 V reverse bias. In addition, a 3 dB bandwidth ( f 3 dB ) of around 30 GHz is achieved at − 3 V , which is the highest reported value among all group III–V and group IV photodetectors working in the 2 μm wavelength range. This work illustrates that a GeSn photodetector has great prospects in 2 μm wavelength optical communication.

Optimizing interferences of DUV lithography on SOI substrates for the rapid fabrication of sub-wavelength features

Scalable fabrication of Si nanowires with a critical dimension of about 100 nm is essential to a variety of applications. Current techniques used to reach these dimensions often involve e-beam lithography or deep-UV (DUV) lithography combined with resolution enhancement techniques. In this study, we report the fabrication of <150 nm Si nanowires from SOI substrates using DUV lithography (λ = 248 nm) by adjusting the exposure dose. Irregular resist profiles generated by in-plane interference under masking patterns of width 800 nm were optimized to split the resulting features into twin Si nanowires. However, masking patterns of micrometre size or more on the same photomask does not generate split features. The resulting resist profiles are verified by optical lithography computer simulation based on Huygens−Fresnel diffraction theory. Photolithography simulation results validate that the key factors in the fabrication of subwavelength nanostructures are the air gap value and the photoresist thickness. This enables the parallel top-down fabrication of Si nanowires and nanoribbons in a single DUV lithography step as a rapid and inexpensive alternative to conventional e-beam techniques.

Thermal characterization of GaN lateral power HEMTs on Si, SOI, and poly-AlN substrates

In this work, the thermal behavior of GaN HEMTs is studied with a three-fold contribution: (i) test structures for resistive thermometry are introduced and manufactured; (ii) subsequently, those are used to perform the on-wafer thermal characterization of small and power HEMTs on SOI, and poly-AlN (QST®) with the aim of comparing the thermal resistance with respect to the reference Si counterpart; (iii) finally, 3D thermal FEM models validated with the experimental results obtained in the previous step are used to perform transient thermal simulations to analyze the effects of substrate thinning, thereby providing as output the thermal impedance (also as equivalent network) and the Safe Operating Area.

Carrier Dynamics in Thin Germanium–Tin Epilayers

The Si-based mid-infrared photonics is an emerging technology in which group-IV germanium–tin (Ge1–xSnx) binary alloys can play a fundamental role in the development of a Si-compatible photonic components including monolithically integrated coherent light sources and detectors, on the same Si or SOI substrate. Although the Ge1–xSnx-on-Si lasers, at low temperatures, have already been demonstrated, the knowledge of the material properties necessary for such device optimization and real-life usage is very limited. In particular, carrier relaxation kinetics, relaxation pathways, and accompanied physical mechanisms, important for the laser’s dynamics, have not been subjected to in-depth research and understanding. In this work, we present detailed spectroscopic studies on photoinjected carrier dynamics in Ge1–xSnx epilayers, as a function of Sn content (6–12%) and temperature (20–300 K), by utilizing time-resolved differential reflectivity and photoluminescence. The latter technique allowed us to track separated electron and hole dynamics with a femtosecond time resolution, while the former experiment exploited a joined electron–hole recombination. This experimental approach allowed us to identify (i) two initial electron relaxation processes after photoexcitation; (ii) radiative electron–hole recombination on below-band gap states; (iii) nonradiative carrier recombination involving the Shockley–Read–Hall mechanism; and (iv) nonradiative recombination through the surface states. The research results significantly expand the knowledge on the initial carrier relaxation dynamics in the Ge1–xSnx epitaxial material. It provides unknown up-to-date kinetic parameters of the initial stage of electron relaxation and further carrier recombination dynamics, unveils the critical role of band gap inhomogeneity for the relaxation dynamics, and highlights the role of below-band gap states that can participate in the light generation process in Ge1–xSnx epilayers.