SOI LDMOS Research Articles

Novel dynamic back-gate control technology for performance improvement in ultrathin double SOI LDMOS

Novel dynamic back-gate control technology for performance improvement in ultrathin double SOI LDMOS

Successful electric field modulation to enhance DC and RF features in SOI LDMOS transistors using a β-Ga2O3 film

Successful electric field modulation to enhance DC and RF features in SOI LDMOS transistors using a β-Ga2O3 film

A Novel High Performance SOI LDMOS with Buried Stepped Gate Field Plate

A Novel High Performance SOI LDMOS with Buried Stepped Gate Field Plate

A Single-Event Burnout Hardened Super-Junction Trench SOI LDMOS with Additional Hole Leakage Paths

In this paper, a novel super-junction trench silicon-on-insulator laterally-diffused metal-oxide-semiconductor (SJT SOI LDMOS) power device with additional hole leakage paths to improve single-event burnout (SEB) performance under high liner energy transfer (LET) is proposed for the first time. The electrical characteristics and SEB performance of the proposed SJT SOI LDMOS are both enhanced effectively. The replacement of a lightly doped N drift region with a heavily doped P pillar and N pillar considerably improves the tradeoff between breakdown voltage (BVDS) and specific on-resistance (Ron,sp). Compared with the conventional trench SOI LDMOS (CT SOI LDMOS), the static figures of merit (FOM, BVDS2/Ron,sp) of the SJT SOI LDMOS increases by 239%. The SEB performance of the SJT SOI LDMOS is significantly improved as the holes induced by the heavy ion can be quickly absorbed to the trench source metal through the heavily doped P+ region and P buried region rather than the base resistor of the parasitic bipolar junction transistor (BJT). The SEB threshold voltage (VSEB) of the CT SOI LDMOS is 58 V (39% of the BVDS) and that of the SJT SOI LDMOS is up to 173 V (87% of the BVDS) at high LET of 1 pC/μm.

A lateral superjunction SOI LDMOS with double-conductive channels

A lateral superjunction SOI LDMOS with double-conductive channels

Research of single event burnout in a high-performance radiation-hardened SOI lateral power MOSFET

In this paper, a 60 V radiation-hardened SOI lateral power MOSFET (LDMOS) device is proposed and single event burnout (SEB) failure mechanism of the device is investigated by Sentaurus simulator. The SOI LDMOS device, with 2 μm drift region and extended N+ drain region, can achieve optimal breakdown voltage (BVDS, 67 V) and specific on-resistance (Ron,sp, 5 mΩ·cm2), while Ron,sp of the device without extended N+ drain is 5.6 mΩ·cm2. Sensitive region of the device for SEB is analyzed and the most sensitive region for SEB is near the center of drift region. The influence of different linear energy transfers (LETs) on SEB threshold voltage is explored and the device can survive at the full drain to source voltage (VDS) biasing of 60 V even for a highly-energetic ion with LET of 1 pC/μm (96 MeV·cm2/mg). Besides, heavily-doped P+ region is inserted on the source side and parameters of source region are optimized to improve SEB tolerance of the device. Second breakdown voltage of the device which correlates with SEB failure threshold is up to 66 V, indicating excellent SEB hardness of the device. Eventually, SEB failure mechanism of the device is investigated in detail and the action of the parasitic npn bipolar junction transistor (BJT) inherent in the device structure is the key to SEB tolerance of the device.

Analysis of radiation effect of a novel SOI-Like LDMOS structure

This study proposes a new SL LDMOS structure similar to a silicon-on-insulator. The P+/N structure is used to replace the buried oxygen layer of traditional SOI LDMOS devices. The N-type layer is made of SiC material, and the highly doped P-type layer is used to partially deplete the SiC layer to achieve the SOI Like effect. At the same time, the highly doped buried layer is formed by ion implantation in the SiC layer to adjust the electric field in the drift region and improve the breakdown voltage. The Silvaco TCAD software is used to conduct a two-dimensional simulation of the proposed structure. The breakdown voltage of the device is 306 V. Compared with the SOI LDMOS under the same withstand voltage, the proposed SL LDMOS has about 32.9% lower the on-resistance and better electrical characteristics. In the study of radiation effects, the burnout threshold of the proposed structure is LET = 0.93 pC/μm and Vd = 222 V, which shows that the device has good anti-single event burnout performance. In the study of the total-ionizing-dose, when the total dose is higher than 119 Krad(Si), the breakdown voltage of the proposed device is significantly higher than that of the SOI LDMOS device. This can effectively address the shortcomings of SOI LDMOS devices regarding the total-ionizing-dose. Therefore, the proposed structure is suitable for application in harsh environments such as those with high radiation.

Field Plate-Adaptive Doping: A Novel Surface Electric Field Optimization Technique for SOI LDMOS With Gate Field Plate

Field Plate-Adaptive Doping: A Novel Surface Electric Field Optimization Technique for SOI LDMOS With Gate Field Plate

Cut-Off Degradation of Output Current Induced by High Fluence Neutron Radiation in High-Voltage Silicon-on-Insulator Lateral Double-Diffused MOSFET

In this letter, a novel cut-off degradation of output current induced by high fluence neutron radiation is investigated for high-voltage silicon-on-insulator lateral double-diffused MOSFET (HV SOI LDMOS). Unlike low/middle fluence, severe current collapse occurs at low drain voltage. Combining experiments and energy band analysis, we reveal that a secondary charge removal effect leads to cut-off degradation, which is closely related to the field enhancement and high-density defects at high neutron fluence. Although the gate channel can be turned on after radiation, below drain threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {DT}}$ </tex-math></inline-formula> ), electron drift is blocked by a potential barrier caused by the local space charge region with low trap occupation rate, rather than the global impact at low fluence. In addition, the influences of structural parameters on the cut-off degradation and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {DT}}$ </tex-math></inline-formula> are studied to guide the rad-hardening design of HV SOI LDMOS.

Deep neural network-based approach for breakdown voltage and specific on-resistance prediction of SOI LDMOS with field plate

Breakdown voltage (BV) and specific on-resistance (R on,sp), are critical indicators to measure the quality of the power device. To improve the device performance, field plate technology has been developed by modifying the electric field distribution. However, the current technology computer-aided design (TCAD) simulation cannot predict the effect of field plate on BV and R on,sp simultaneously, and the operation process is complicated. This paper proposes a deep neural network (DNN)-based model instead of TCAD to predict the effect of field plates on BV and R on,sp of silicon on insulator lateral double diffused metal oxide semiconductor. The experimental results show that, compared with TCAD simulation, the average deviation for BV and R on,sp is 5.06% and 2.55%, respectively. Also, the time for BV prediction is accelerated significantly up by 1.23 × 105. Our DNN model provides a potential direction to predict device performance with higher efficiency.

Analysis of novel silicon based lateral power devices with floating substrate on insulator

With the rapid development of the traditional inorganic semiconductor industry, the improvement of its electrical performance is gradually approaching to the limit. It is difficult to continue to improve the performance, lessen the size, and reduce the cost. Therefore, organic semiconductor materials and devices with simple process and low cost have been found and gradually become a new research hotspot. Although organic semiconductor materials and devices are developing rapidly, their electrical properties, such as carrier mobility, are considerably inferior to those of inorganic semiconductors, and their research direction and application prospect are relatively fixed and single. They are developed only in display, sensing, photoelectric conversion and other fields, but the researches on switching power devices, integrated circuits and other fields are still relatively blank. At the same time, power devices are used only in the field of inorganic semiconductors. Therefore, in order to expand the research direction of organic semiconductors and power devices at the same time, a novelsilicon on insulator lateral double-diffused metal oxide semiconductor (SOI LDMOS)power device is reported in this paper. Unlike the SOI LDMOS power devices in traditional inorganic semiconductors, this novel device can be used in the field of organic semiconductors by combining with insulated flexible substrates, which provides a new possibility for the research direction of organic semiconductors. In this paper, both simulation and experiment verify that specific on-resistance (&lt;i&gt;R&lt;/i&gt;&lt;sub&gt;ON,sp&lt;/sub&gt;) and threshold voltage (&lt;i&gt;V&lt;/i&gt;&lt;sub&gt;TH&lt;/sub&gt;) do not change significantly when the conventional SOI LDMOS lacks the substrate electrode, but the breakdown voltage decreases by about 15% due to the absence of the substrate electrode or the longitudinal electric field. In response to this phenomenon, in this paper proposed is a novel SOI LDMOS power device that possesses surface substrate electrodes and drift zone oxide trenches. This novel device can provide electrodes for the substrate again, optimize the horizontal and vertical electric field, and significantly change neither of the &lt;i&gt;R&lt;/i&gt;&lt;sub&gt;ON,sp&lt;/sub&gt; and the &lt;i&gt;V&lt;/i&gt;&lt;sub&gt;TH&lt;/sub&gt;. At the same time, the breakdown voltage (BV) of conventional SOI LDMOS is increased by 57.54%, which alleviates the adverse effects caused by the application in the field of organic semiconductors. This novel SOI LDMOS power device provides the possibility of applying traditional power semiconductors to the research of organic semiconductors, and has innovative significance for expanding the organic semiconductor research.

Novel High-K SOI LDMOS with N+ Buried Layer

A novel high-K dielectric trench SOI LDMOS with an interface highly doped N buried layer (HKHN SOI LDMOS) is proposed. The devices are characterized with a high-K dielectric material (HK) introduced in the drift region and a high doping concentration of N existed below the HK trench (HKHN). First, the HK material causes assistant depletion in the N-drift region to increase doping concentration of the drift region (N d) and further improve the electric field (E-field) distribution. Second, the highly doped N buried layer below the interface of the HK trench can provide a low on-resistance passage and shorten the ionization integral path to enhance bulk field (ENBULF). Both the high drift region doping concentration and low on-resistance passage can reduce the specific on-resistance (R on,sp). Meanwhile, a higher breakdown voltage (BV) can be obtained by an optimized electric field distribution and a shortened ionization integration path. The new device can achieve high BV, low R on,sp and excellent figure of merit (FOM = BV 2/R on,sp). The BV of the HKHN SOI LDMOS is 552 V with R on,sp of 29.46 mΩ cm2 and FOM of 10.343 MW cm−2.

Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers

Double silicon drift layers are used to reduce the specific on-resistance (Ron,sp) for a trench-gate-integrated lateral double-diffused MOSFET (DDL TG LDMOS) based on SOI technology in this paper. A trench-gate is incorporated into the oxide trench, a n-type drift layer with a high doping concentration is introduced on the topside of the original drift layer around the oxide trench, and a p-type pillar layer with a high doping concentration is inserted between the dual drift layers. First, the incorporated trench-gate constitutes dual current conduction channels, which decreases the Ron,sp. Second, the whole electric fields on the device surface and around the oxide trench are modulated on the basis of RESURF condition, leading to a higher breakdown voltage (BV) at off-state. Finally, the doping concentration of the drift layers is increased by an assistant depletion effect from the p-pillar, which not only improves the BV but also reduces the Ron,sp. Consequently, compared with those of the conventional trench SOI LDMOS on the same drift region of 18 μm and top silicon layer of 25 μm, a higher BV of 477 V and a lower Ron,sp of 32.1 mΩ∙cm2 are obtained for the DDL TG SOI LDMOS, while BV is improved by 33.5% and Ron,sp is reduced by 92.9%, respectively.

Effect of Drift Length on Shifts in 400-V SOI LDMOS Breakdown Voltage Due to TID

Recently, Shu et al. published “Numerical and Experimental Investigation of TID Radiation Effect on the Breakdown Voltage of 400 V SOI NLDMOS.” This short article is an extension of that earlier article. The breakdown voltage of 400-V silicon-on-insulator n-channel laterally diffused metal-oxide semiconductor field-effect transistors with different drift region lengths are examined after exposure to total ionizing dose. The variation observed is analyzed using technology computer-aided design simulation.

An Analytical Breakdown Model for the SOI LDMOS With Arbitrary Drift Doping Profile by Using Effective Substrate Voltage Method

To elaborate on the relationship between sophisticated 2-D doping profile of drift region and device's breakdown behavior, a unified analytical model for the SOI LDMOS is developed in this paper. The Effective Substrate Voltage (ESV) concept is proposed so that the derivation of electric field and breakdown voltage can be simplified significantly. The ESV indicates that the influence of 2-D doping in the drift region can be equivalent to a virtual substrate potential. By using the proposed model, the role of 2-D drift doping, both continuous or discrete doping profile, in SOI LDMOSs' off-state breakdown behavior is investigated along with the TCAD simulations and experimental results. The good agreement between the analytical, measured and simulated results validates the accuracy of the developed model. A unified RESURF criterion is derived to idealize the electric field in the drift region and therefore maximize the breakdown voltage by optimizing the lateral and vertical drift doping profiles and geometric parameters. The proposed approach provides a universally applicable tool to explore the breakdown mechanism of SOI LDMOS with various drift doping profiles.

Analytical model of buried air partial SOI LDMOS

A two-dimensional analytical model has been proposed for the Air Partial Silicon-On-Insulator (APSOI) LDMOS in this paper for the first time. The analytical solutions for the device are derived on the basis of the two-dimensional Poisson equation. An electric field modulation model that takes into account both the lateral and vertical electric field is proposed. The surface electric field is modulated through the variation of buried layer parameters with electric field modulation effect. Under the same simulation parameters, the breakdown voltage of APSOI LDMOS is 140% higher than that of traditional SOI and 93% higher than that of the traditional Silicon-On-Insulator structure with Step-Doped Drift region (SDDSOI). Also, it has been researched that the role of the key structural parameter in device performance is consistent with the expected results of the model, which proves that the effectiveness of electric field modulation effect and our model has guiding significance for device parameter optimization.

PSJ LDMOS with a VK dielectric layer

A partial super junction lateral double-diffused metal–oxide–semiconductor field-effect transistor with a variable- k dielectric layer (PSJ VK LDMOS) is proposed in this Letter. Low- k material and PSJ are introduced into the device. PSJ provides a low-resistance channel to reduce the specific on-resistance ( R on,sp ). Furthermore, according to an enhanced dielectric layer field, low- k buried layer can sustain the high breakdown voltage (BV). To eliminate substrate-assisted depletion effect and improve the lateral BV of the proposed structure, the charge compensation layer in the device adopts a variation of lateral doping technique and is combined with the N pillar in PSJ. Ultimately, the simulation results show that BV of 795.5 V and the figure of merit (FOM) of 6.1 MW cm −2 are achieved for PSJ VK LDMOS. BV and FOM are enhanced by 71.4 and 81.1%, respectively, compared with con. PSJ SOI LDMOS with the drift region length of 46.5 μm. Furthermore, R on,sp of 103.4 mΩ cm 2 is reduced by 31.2% compared with the ‘silicon limit’ at the same BV class, which breaks the ‘silicon limit’.

Total-Ionizing-Dose Irradiation-Induced Dielectric Field Enhancement for High-Voltage SOI LDMOS

Breakdown voltage (BV) shifting behavior induced by total-ionizing-dose (TID) irradiation is investigated for high-voltage SOI LDMOS, in this letter. The BV increase caused by irradiation is present for the first time, and the degradation mechanism is revealed by modeling and simulation. Irradiation-induced electric field modulation exerts an impact on the competition between the lateral BV and vertical BV and results in BV shifting. The dielectric field is enhanced by irradiation-induced positive oxide trapped charges in the BOX layer, which is responsible for the BV increasing after irradiation. A TID radiation hardening approach is proposed so that the lateral BV is required to be properly higher than vertical BV instead of pursuing equality.

Performance analysis of a novel trench SOI LDMOS with centrosymmetric double vertical field plates

Abstract A novel trench SOI LDMOS with centrosymmetric double vertical field plates structure (CDVFPT SOI LDMOS) is proposed in this paper. The 2-D device simulator MEDICI is used to investigate the characteristics of the proposed structure. Compared with the conventional trench SOI LDMOS (CT SOI LDMOS), the optimized device shows an obvious reduction in the specific on-resistance (Ron,sp) when its breakdown voltage (BV) is enhanced due to the introduction of centrosymmetric double vertical field plates structure. And when compared to previous device with floating vertical field plate trench SOI LDMOS (FVFPT SOI LDMOS), the overall performance of CDVFPT SOI LDMOS is also promoted. According to the simulation results, compared to a CT SOI LDMOS, the BV of CDVFPT SOI LDMOS increases from 188 V to 234 V. The Ron,sp, however, decreases from 2.30 mΩ·cm2 to 1.24 mΩ·cm2. In addition, the maximum lattice temperature at 1 mW/μm2 is slightly reduced.

Improved SOI LDMOS performance by using a partial stepped polysilicon layer as the buried layer

A novel SOI LDMOS with a stepped polysilicon compound buried layer (SP-CBL) is proposed in this paper. In the SP-CBL SOI LDMOS, a stepped polysilicon layer is introduced into the buried layer. Firstly, SP-CBL brings in two new electric field peaks and modulates the electric field of drift region and obviously promotes the breakdown voltage (BV). Secondly, SP-CBL reduces the thickness of the top buried oxide layer, and the doping concentration of the drift region is thus increased according to the RESURF condition. The specific on-resistance (Ron,sp) is reduced. In addition, the polysilicon conducts heat more efficiently than SiO2, relieving the self-heating effect to some extent. The effects of critical structure parameters on the device performances are investigated. Ultimately, compared with the partial compound buried layer structure (P-CBL SOI LDMOS), BV of SP-CBL SOI LDMOS is enhanced by 13.7% and Ron,sp is reduced by 15% at the same device dimension, and the maximum temperature is dropped by 7.2 K at the power of 1 mW/μm. Compared with the conventional SOI LDMOS (C-SOI LDMOS), BV is enhanced by 66.3%, Ron,sp is reduced by 52.4%, and temperature is depressed by 11.4 K.