Soft Error Performance Research Articles

Assessment of Radiation-Induced Soft Errors on Lightweight Cryptography Algorithms Running on a Resource-Constrained Device

Most safety-critical edge-computing devices rely on lightweight cryptography (LWC) algorithms to provide security at minimum power and performance overhead. LWC algorithms are traditionally embedded as a hardware component, but with the advance of the Internet of Things (IoT), emerging firmware is more likely to support cryptography algorithms to comply with different security levels and industry-standards. This is the first work to present the soft error assessment of five cryptography algorithms executing in a low-power microprocessor running under neutron radiation, considering electronic code book (ECB) and counter (CTR) mode of operation implementations. Results obtained from two neutron radiation tests suggest that: ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i> ) the NOEKEON algorithm gives the best relative soft error reliability, performance, power efficiency and memory footprint utilisation trade-offs between the five algorithms considering both ECB and CTR implementations, and ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ii</i> ) cryptography solutions based on the counter mode of operation present better FIT rate for silent data corruption (SDC) and crash w.r.t. ECB implementations.

Numerical Study on SEU Performance of Strain Engineered 6T-SRAM Cells

In this work, the impact of shallow trench isolation (STI) and dual stress liner (DSL) -induced stresses on soft error performance of 30-nm gate length Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET)-based 6T-SRAM cells is studied using process and device simulations. Under nine different stress combinations, i.e., nine different SRAMs, our simulation results show that the stresses introduced from STI and DSL enhance the soft error performance of the cells significantly.

Soft error study on junctionless silicon nanotube FET based 6T SRAM cell

In this work, the response of Junctionless Silicon Nanotube FET (JL SiNT FET) to the heavy ion irradiation and the soft error performance of JL SiNT FET based SRAM circuit are investigated using 3D numerical simulations. The impact of single event transient (SET) is studied at different locations of junctionless SiNT with different incident angles to identify the sensitive location of the device. After SET analysis, JL SiNT FET based 6T SRAM cell is studied for single event upset (SEU). Heavy ion study of JL SiNT FET is compared with junction based SiNT FET. The simulation result shows that the threshold linear energy transfer (LETth) of JL SiNT FET based SRAM is approximately three times lesser than the junction based SiNT FET SRAM.

GPU Architecture Aware Instruction Scheduling for Improving Soft-Error Reliability

The demand for low-power and high-performance computing has been driving the semiconductor industry for decades. The semiconductor technology has been scaled down to satisfy these demands. At the same time, the semiconductor technology has faced severe reliability challenges like soft-error. Research has been conducted to improve the soft-error reliability of the GPU, which has been improved by using various methodologies such as redundancy methodologies. However, the GPU compiler has yet to be considered for improving the soft-error reliability of the GPU. In this paper, in order to improve the soft-error reliability of the GPU, we propose a novel GPU architecture aware compilation methodology. The proposed methodology jointly considers the parallel behavior of the GPU hardware and the applications, and minimizes the vulnerability of the GPU applications during instruction scheduling. In addition, the proposed methodology is able to complement any hardware based soft-error reliability improvement techniques. We compared our compilation methodology with the state-of-the-art soft-error reliability aware techniques and the performance aware instruction scheduling. We have injected the soft-errors during the experiments and have compared the number of correct executions that have no erroneous output. Our methodology requires less performance and power overhead than the state-of-the-art soft-error reliability methodologies in most cases. Compilation time overhead of our methodology is 8.13 seconds on average. The experimental results show that our methodology improves the soft-error reliability by 23 percent and 12 percent (up to 64 percent and 52 percent) compared to the state-of-the-art soft-error reliability and performance aware compilation techniques, respectively. Moreover, we have shown that the soft-error reliability of a GPU is not related to the performance, but to the fine-grained timing behavior of an application.

Modeling and Experimental Study of Soft Error Propagation Based on Cellular Automaton

Aiming to estimate SEE soft error performance of complex electronic systems, a soft error propagation model based on cellular automaton is proposed and an estimation methodology based on circuit partitioning and error propagation is presented. Simulations indicate that different fault grade jamming and different coupling factors between cells are the main parameters influencing the vulnerability of the system. Accelerated radiation experiments have been developed to determine the main parameters for raw soft error vulnerability of the module and coupling factors. Results indicate that the proposed method is feasible.

Radiation performance of planar junctionless devices and junctionless SRAMs

The objective of this work is to analyze the radiation performance of the planar junctionless devices and junctionless device-based SRAMs. Bulk planar junctionless transistor (BPJLT) and silicon-on-insulator planar junctionless transistors (SOIPJLT) under heavy ions irradiation have been studied using TCAD simulations. 6T-SRAM cells built up of BPJLTs and SOIPJLTs have been investigated for their soft error performance. Even though the bipolar amplification of the SOIPJLT is more compared to BPJLT, the soft error performance of the SOIPJLT SRAM is better compared to BPJLT SRAM.

Heavy-ion irradiation study in SOI-based and bulk-based junctionless FinFETs using 3D-TCAD simulation

In this paper, SOI-based and bulk-based junctionless FinFETs subjected to heavy–ion irradiation are scrutinized using 3D-TCAD simulation. Since the junctionless devices need heavy doping concentrations, devices with various fin dopings are studied for their radiation performance. Transient drain current device simulations depict higher disturbances in bulk devices. Bipolar amplification is higher in SOI devices. The soft error performances of the SRAM cells based on the above devices are also explored. Even though the SOI devices have higher bipolar amplification than the bulk device, they show better soft error performance in SRAMs.

Effect of Underlap and its Soft Error Performance in 30 nm Junctionless-based 6T-SRAM Cell

As CMOS device is scaling down significantly, the sensitivity of Integrated Circuits (ICs) to Single Event Upset (SEU) radiation increases. The Sensitivity of ICs to soft errors emerge as reliability threat which motivates significant interest in the development of various techniques both at the device and circuit level for SEU hardness in SRAM memories. To facilitate the scaling the concept of underlap Gate-Source/Drain (G-S/D) was suggested in the literature. L un is one of the sensitive geometrical parameter considered to differ from 1 nm to 5 nm in a SEU radiating environment. The effect of Gate-Source/Drain underlap (L un ) on soft error performance in 30 nm Junctionless Transistor (JLT) based on 6T-SRAM cell has been examined through extensive mixed mode-device and circuit simulations using TCAD. The critical dose observed in JLT based 6T-SRAM with L un ranging from 1 nm to 5 nm to flip the cell is given by Linear Energy Transfer (LET) between 0.05 to 0.06 pC/µm. The simulation result analyzes electrical and SEU radiation parameters to study its impact on JLT based 6T-SRAM cell.

Effect of underlap and soft error performance in 30 nm FinFET-based 6T-SRAM cells with simultaneous and independent driven gates

The effect of Gate-Source/Drain underlap (L un) on soft error performance in 30 nm common double gate-FinFET (simultaneously driven gates) and independent double gate-FinFET (independently driven gates) have been examined through extensive mixed mode-device and circuit simulations using Sentaurus TCAD. Four different 6T-SRAM topologies, one simultaneously driven double gate-FinFET and three independently driven double gate-FinFETs-based topologies namely Flex-V TH, Flex-PG, and PG-SN are chosen to study the geometrical parameter L un and also to calculate their soft error performance. When L un increases, current decreases due to increase in parasitic series resistance. The simulation results reveal that L un increase in independently driven double gate-FinFETs in place of access devices in 6T-SRAM does not degrade the soft error performance significantly whereas the L un increase inside the cell, in the inverters, degrade the performance significantly.

A first-order mechanistic model for architectural vulnerability factor

Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probability that a radiation-induced fault in a hardware structure will manifest as an error at the program output. AVF estimation requires detailed microarchitectural simulations which are time-consuming and typically present aggregate metrics. Moreover, it requires a large number of simulations to derive insight into the impact of microarchitectural events on AVF. In this work we present a first-order mechanistic analytical model for computing AVF by estimating the occupancy of correct-path state in important microarchitecture structures through inexpensive profiling. We show that the model estimates the AVF for the reorder buffer, issue queue, load and store queue, and functional units in a 4-wide issue machine with a mean absolute error of less than 0.07. The model is constructed from the first principles of out-of-order processor execution in order to provide novel insight into the interaction of the workload with the microarchitecture to determine AVF. We demonstrate that the model can be used to perform design space explorations to understand trade-offs between soft error rate and performance, to study the impact of scaling of microarchitectural structures on AVF and performance, and to characterize workloads for AVF.

Soft error study in double gated FinFET-based SRAM cells with simultaneous and independent driven gates

Common double gate-FinFET (simultaneously driven gates) and independent double gate-FinFET (independently driven gates) based 6T-SRAM cells are studied in this paper for their Single Event Upset (SEU) or soft error performance using 3D TCAD simulations. Four different topologies, one common double gate-FinFET-based topology and three independent double gate-FinFET-based topologies namely, Flex-VTH, Flex-PG, and PG-SN are studied to find out their minimum radiation dose required to flip SRAM cell. The simulation results reveal that the independent double gate FinFETs in place of access devices in 6T-SRAM does not degrade the soft error performance significantly whereas the independent gate devices inside the cell, in the inverters, degrades the performance significantly.

Design Framework for Soft-Error-Resilient Sequential Cells

This paper presents a design framework for soft-error-resilient sequential cells, by introducing a new sequential cell called LEAP-DICE and evaluating it against existing circuit techniques in the “soft error resilience-power-delay-area” design space in an 180 nm CMOS test chip. LEAP-DICE, which employs both circuit and layout techniques, achieved the best soft error performance with a 2,000X improvement over the reference D flip-flop with moderate design costs. This study also discovered new soft error effects related to operating conditions.

Specification and Verification of Soft Error Performance in Reliable Internet Core Routers

This paper presents a methodology for developing a specification for soft error performance of an integrated hardware/software system that must achieve highly reliable operation. The methodology enables tradeoffs between reliability and cost to be made during the early silicon design and SW architecture phase. An accelerated measurement technique using neutron beam irradiation is also described that ties the final system performance to the reliability model and specification. The methodology is illustrated for the design of a line card for an internet core router.

Detection mechanisms employing single event upsets in dynamic random access memories used as radiation sensors

A hardware system is being designed and constructed for the detection of neutrons, with a view to using it in neutron imaging and elemental analysis. A feasibility study was initially carried out to demonstrate that dynamic Random Access Memories (dRAMs) can be used as heavy charged particle detectors and furthermore be made sensitive to neutrons. We are interested, however, in constructing a detector that will be position sensitive, and hence carried out experiments to investigate the relative sensitivity of specific elements within the dRAM chips. The findings from these initial system tests highlight the usefulness of such a device as a position sensitive radiation detector. This paper aims to explain and give a review of most aspects concerning the soft error (SE) performance using dRAM as a radiation sensor.

Parameter-free, predictive modeling of single event upsets due to protons, neutrons, and pions in terrestrial cosmic rays

In this paper we present a new approach and a computer software for modeling single event upsets. This model, named Soft Error Monte Carlo Model (SEMM), does not need any experimental inputs or any parameter fitting. It is intended to be a design tool for chip designers when they want to optimize their designs for soft error hardness and performance. The paper focuses on terrestrial cosmic rays that cause single event upsets. Details of the nuclear modeling and of the coupled device-circuit modeling are presented. Also presented are the comparison of SEMM predictions against measurements of single event upset rate in proton beam experiments and in computer main frame field tests performed at high ground elevations. We also present some proton-pion comparisons that are relevant to single event upsets.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Alpha particle induced soft errors in NMOS RAMS: a review

The paper aims to explain the alpha particle induced soft error phenomenon using the NMOS dynamic random access memory (RAM) as a model. It discusses some of the many techniques experimented with by manufacturers to overcome the problem, and gives a review of the literature covering most aspects of soft errors in dynamic RAMs. Finally, the soft error performance of current dynamic RAM and static RAM products from several manufacturers are compared.

Characterization of Denuded Zones in Silicon Wafers

ABSTRACTDifferent techniques are presented for the characterization of the two-layered system consisting of a precipitate-free zone and a precipitated zone, generated in CZ-grown silicon wafers by thermal processing. The diffusion length profile can be determined by surface photovoltage characteristics; measurements of the collection efficiency for excess carriers generated by alpha particles gives relevant information about the soft error performance. Finally, oxygen depth profiling by SIMS is discussed. Results are shown and compared with damage patterns obtained from cleavage face etching.