Effect of underlap and soft error performance in 30 nm FinFET-based 6T-SRAM cells with simultaneous and independent driven gates

Abstract

The effect of Gate-Source/Drain underlap (L un) on soft error performance in 30 nm common double gate-FinFET (simultaneously driven gates) and independent double gate-FinFET (independently driven gates) have been examined through extensive mixed mode-device and circuit simulations using Sentaurus TCAD. Four different 6T-SRAM topologies, one simultaneously driven double gate-FinFET and three independently driven double gate-FinFETs-based topologies namely Flex-V TH, Flex-PG, and PG-SN are chosen to study the geometrical parameter L un and also to calculate their soft error performance. When L un increases, current decreases due to increase in parasitic series resistance. The simulation results reveal that L un increase in independently driven double gate-FinFETs in place of access devices in 6T-SRAM does not degrade the soft error performance significantly whereas the L un increase inside the cell, in the inverters, degrade the performance significantly.