SoC Design Research Articles

SmartDampener: An Open Source Platform for Sport Analytics in Tennis

In this paper, we introduce SmartDampener, an open-source tennis analytics platform that redefines the traditional understanding of vibration dampeners. Traditional vibration dampeners favored by both amateur and professional tennis players are utilized primarily to diminish vibration transmission and enhance racket stability. However, our platform uniquely merges wireless sensing technologies into a device that resembles a conventional vibration dampener, thereby offering a range of tennis performance metrics including ball speed, impact location, and stroke type. The design of SmartDampener adheres to the familiar form of this accessory, ensuring that (i) it is readily accepted by users and robust under real-play conditions such as ball-hitting, (ii) it has minimal impact on player performance, (iii) it is capable of providing a wide range of analytical insights, and (iv) it is extensible to other sports. Existing computer vision systems for tennis sensing such as Hawk-eye and PlaySight, rely on hardware that costs millions of US dollars to deploy with complex setup procedures and is susceptible to lighting environment. Wearable devices and other tennis sensing accessories, such as Zepp Tennis sensor and TennisEye, using intrusive mounting locations, hinder user experience and impede player performance. In contrast, SmartDampener, a low-cost and compact tennis sensing device, notable for its socially accepted, lightweight and scalable design, seamlessly melds into the form of a vibration dampener. SmartDampener exploits opportunities in SoC and form factor design of conventional dampeners to integrate the sensing units and micro-controllers on a two-layer flexible PCB, that is bent and enclosed inside a dampener case made of 3D printing TPU material, while maintaining the vibration dampening feature and further being enhanced by its extended battery life and the inclusion of wireless communication features. The overall cost is $9.42, with a dimension of 21.4 mm × 27.5 mm × 9.7 mm (W × L × H) and a weight of 6.1 g and 5.8 hours of battery life. In proof of SmartDampener's performance in tennis analytics, we present various tennis analytic applications that exploit the capability of SmartDampener in capturing the correlations across string vibration, and racket motion, including the estimation of ball speed with a median error of 3.59 mph, estimation of ball impact location with accuracy of 3.03 cm, and classification of six tennis strokes with accuracy of 96.75%. Finally, extensive usability studies with 15 tennis players indicate high levels of social acceptance of form factor design for the SmartDampener dampener in comparison with alternative form factors, as well as its capability of sensing and analyzing tennis stroke in an accurate and robust manner. We believe this platform will enable exciting applications in other sports like badminton, fitness tracking, and injury prevention.

A Case Study on Formal Sequential Equivalence Checking based Hierarchical Flow Setup towards Faster Convergence of Complex SOC Designs

A Case Study on Formal Sequential Equivalence Checking based Hierarchical Flow Setup towards Faster Convergence of Complex SOC Designs

Design and FPGA Implantation of SoC for Multimedia Applications Using Deep Learning Based RNN Architecture for Low Power and High Throughput

Design and FPGA Implantation of SoC for Multimedia Applications Using Deep Learning Based RNN Architecture for Low Power and High Throughput

AutoModel: Automatic Synthesis of Models From Communication Traces of SoC Designs

AutoModel: Automatic Synthesis of Models From Communication Traces of SoC Designs

An SoC Design for Future Mobile DNA Detection

An SoC Design for Future Mobile DNA Detection

A Novel Approach to Managing System-on-Chip Sub-Blocks Using a 16-Bit Real-Time Operating System

Embedded computers are ubiquitous in products across various industries, including the automotive and medical industries, and in consumer goods such as appliances and entertainment devices. These specialized computing systems utilize Systems on Chips (SoCs), devices that are made up of one or more main microprocessor cores. SoCs are augmented with sub-blocks that perform dedicated tasks to support the system. Sub-blocks contain custom logic or small-footprint microprocessors, depending upon their complexity, and perform support functions such as clock generation, device testing, phase-locked loop synchronization and peripheral management for interfaces such as a Universal Serial Bus (USB) or Serial Peripheral Interface (SPI). SoC designers have traditionally obtained sub-blocks from commercial vendors. While these sub-blocks have well-defined interfaces, their internal implementations are opaque. Without visibility of the specifics of the implementation, SoC designers are limited to the degree to which they can optimize these off-the-shelf sub-blocks. The result is that power and area constraints are dictated by the design of a third-party vendor. This work introduces a novel idea: using an open-source, small, multitasking, real-time operating system inside an SoC sub-block to manage multiple processes, thereby conserving code space. This OS is TurbOS, a new operating system whose primary goal is to provide the highest performance using the least amount of space. It is written in the assembly language of a new pipelined 16-bit microprocessor developed at the University of Florida, the Turbo9. TurbOS is derived from and incorporates the design benefits of an existing operating system called NitrOS-9, and reduces the code size from its progenitor by nearly 20%. Furthermore, it is over 80% smaller than the popular FreeRTOS operating system. TurbOS delivers a rich feature set for managing memory and process resources that are useful in SoC sub-block applications in an extremely small footprint of only 3 kilobytes.

Fpga-based SoC design for real-time facial point detection using deep convolutional neural networks with dynamic partial reconfiguration

Fpga-based SoC design for real-time facial point detection using deep convolutional neural networks with dynamic partial reconfiguration

High-Speed CNN Accelerator SoC Design Based on a Flexible Diagonal Cyclic Array

The latest convolutional neural network (CNN) models for object detection include complex layered connections to process inference data. Each layer utilizes different types of kernel modes, so the hardware needs to support all kernel modes at an optimized speed. In this paper, we propose a high-speed and optimized CNN accelerator with flexible diagonal cyclic arrays (FDCA) that supports the acceleration of CNN networks with various kernel sizes and significantly reduces the time required for inference processing. The accelerator uses four FDCAs to simultaneously calculate 16 input channels and 8 output channels. Each FDCA features a 4 × 8 systolic array that contains a 3 × 3 processing element (PE) array and is designed to handle the most commonly used kernel sizes. To evaluate the proposed CNN accelerator, we mapped the widely used YOLOv5 CNN model and evaluated the performance of its implementation on the Zynq UltraScale+ MPSoC ZCU102 FPGA. The design consumes 249,357 logic cells, 2304 DSP blocks, and only 567 KB BRAM. In our evaluation, the YOLOv5n model achieves an accuracy of 43.1% (mAP@0.5). A prototype accelerator has been implemented using Samsung’s 14 nm CMOS technology. It achieves 1.075 TOPS, a peak performance with a 400 MHz clock frequency.

Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm

A new area model for estimating the layout area of switch blocks is introduced in this work. The model is based on a realistic layout strategy. As a result, it not only takes into consideration the active area that is needed to construct a switch block but also the number of metal layers available and the actual dimensions of these metals. The model assigns metal layers to the routing tracks in a way that reduces the number of vias that are needed to connect different routing tracks together while maintaining the tile-based structure of FPGAs. It also takes into account the wiring area required for buffer insertion for long wire segments. The model is evaluated based on the layouts constructed in the ASAP7 FinFET 7nm Predictive Design Kit. We found that the new model, while specific to the layout strategy that it employs, improves upon the traditional active-based area estimation models by considering the growth of the metal area independently from the growth of the active area. As a result, the new model is able to more accurately estimate the layout area by predicting when the metal area will overtake the active area as the number of routing tracks is increased. This ability allows the more accurate estimation of the true layout cost of FPGA fabrics at the early floor planning and architectural exploration stage; and this increase in accuracy can encourage a wider use of custom FPGA fabrics that target specific sets of benchmarks in future SOC designs. Furthermore, our data indicate that the conclusions drawn from several significant prior architectural studies remain to be correct under FinFET geometries and wiring area considerations despite their exclusive use of active-only area models. This correctness is due to the small channel widths, around 30–60 tracks per channel, of the architectures that these studies investigate. For architectures that approach the channel width of modern commercial FPGAs with more than 100–200 tracks per channel, our data show that wiring area models justified by detailed layout considerations are an essential addition to active area models in the correct prediction of the implementation area of FPGAs.

Low Power Embedded SoC Design

Low Power Embedded SoC Design

Elastic Gateway SoC design: A HW-centric architecture for inline In-Vehicle Network processing

The concepts of future mobility such as autonomous, connected, electric and shared vehicles are bringing a huge revolution to the automotive sector. We are seeing technologies typical from data centers fully embedded into vehicles, shifting from a mechanical-centric product, to an electronics-centric one. All the sensors and actuators embedded in vehicles need to exchange data in real time, in a safe and reliable way. As a result, the field of in-vehicle network (IVN) processing is currently an active research area. In previous work, we derived the requirements of future vehicle network processors and analyzed the state of the art of network processing platforms. From our study we concluded that there is currently no solution available capable of fulfilling all the requirements with the right level of performance. Now, in this work, we evaluate the novel Elastic Gateway (eGW) architecture which aims at fulfilling this gap, advancing towards future Gateway System/Network on Chip (SoC/NoC) solutions. Elastic Gateway SoC concept aims at synthesizing a scalable and future proof architecture embracing all new and already established functions and features demanded in a zonal gateway controller for the new era of mobility. It is composed of a set of configurable IP cores that allow for a full HW-based datapath implementation targeting good enough Quality of Service (QoS) and the minimum possible latency. We provide details of the internal architecture and how the different technologies required in future IVNs are integrated in eGW. With this, we are able to show how eGW meets the requirements of future network processing devices, enabling thus the current revolution.

GMM-Based Speaker Verification System with Hardware MFCC in SoC Design

GMM-Based Speaker Verification System with Hardware MFCC in SoC Design

Optimized Design of C8051F040 SOC Based Automotive Engine Tester

Automotive engine tester is an important instrumentation for performance testing and fault diagnosis of automotive engines. How to make real-time effective and fast engine testing has become a key technology for automotive engine testing. This paper further optimizes the C8051F040 SOC's automotive engine tester based on the use of a cost-effective C8051F040 system-on-chip as the core, supplemented by relevant sensor sets and other functional components, to achieve the design requirements of a low-cost, high-performance instrument. The overall performance of the system is superior and versatile through prototype testing.

Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis

Hardware Trojans that have the capability to change the computed functional output in intellectual property (IP) cores, integrated into computing systems can be a vital reliability concern in the context of correct system operation. Therefore, determining an optimal Trojan-resistant hardware design architecture that considers multi-objective orthogonal parameters such as area and delay is crucial. This paper presents a novel exploration of optimal hardware IP core design methodology with Trojan defense capability (i.e., detection and isolation) during high level synthesis (HLS) that provides isolation of functional Trojan in a system design to ensure reliable and correct functional behavior. The proposed methodology is robust and provides the capability to yield the correct output value using HLS-based triple modular redundancy (TMR) logic and a distinct multivendor allocation policy. Therefore, the proposed HLS methodology can generate an optimal hardware IP core/system-on-chip (SoC) design with functional Trojan defense capability. The paper presents an overall flow of the proposed methodology along with a demonstrative case study on designing optimal Trojan resistant finite impulse response filter (FIR) hardware SoC design. Results of the proposed approach are evaluated in terms of design cost, convergence time, security and optimality analysis, and comparison with prior works. The proposed approach is able to generate fully functional Trojan-resistant optimal SoC designs with minimum overhead, as evident from optimality analysis and design cost.

Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design

Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design

Open-Source HW/SW Co-Simulation Using QEMU and GHDL for VHDL-Based SoC Design

Hardware/software co-simulation is a technique that can help design and validate digital circuits controlled by embedded processors. Co-simulation has largely been applied to system-level models, and tools for SystemC or SystemVerilog are readily available, but they are either not compatible or very cumbersome to use with VHDL, the most commonly used language for FPGA design. This paper presents a direct, simple-to-use solution to co-simulate a VHDL design together with the firmware (FW) that controls it. It aims to bring the power of co-simulation to every digital designer, so it uses open-source tools, and the developed code is also open. A small patch applied to the QEMU emulator allows it to communicate with a custom-written VHDL module that exposes a CPU bus to the digital design, controlled by the FW emulated in QEMU. No changes to FW code or VHDL device code are required: with our approach, it is possible to co-simulate the very same code base that would then be implemented into an FPGA, enabling debugging, verification, and tracing capabilities that would not be possible even with the real hardware.

ObNoCs : Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks

Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineering the NoC topology and routing logic. In this paper, we develop an infrastructure, ObNoCs , for protecting NoC fabrics against such attacks. ObNoCs systematically replaces router connections with switches that can be programmed after fabrication to induce the desired topology. Our approach provides provable redaction of NoC functionality: switch configurations induce a large number of legal topologies, only one of which corresponds to the intended topology. We implement the ObNoCs methodology on Intel Quartus™ Platform, and experimental results on realistic SoC designs show that the architecture incurs minimal overhead in power, resource utilization, and system latency.

Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework

The complexity of manycore System-on-chips (SoCs) is growing faster than our ability to manage them to reduce the overall energy consumption. Further, as SoC design moves toward three-dimensional (3D) architectures, the core's power density increases leading to unacceptable high peak chip temperatures. In this article, we consider the optimization problem of dynamic power management (DPM) in manycore SoCs for an allowable performance penalty (say, 5%) and admissible peak chip temperature. We employ a machine learning– (ML) based DPM policy, which selects the voltage/frequency levels for different cluster of cores as a function of the application workload features such as core computation and inter-core traffic, and so on. We propose a novel learning-to-search (L2S) framework to automatically identify an optimized sequence of DPM decisions from a large combinatorial space for joint energy-thermal optimization for one or more given applications. The optimized DPM decisions are given to a supervised learning algorithm to train a DPM policy, which mimics the corresponding decision-making behavior. Our experiments on two different manycore architectures designed using wireless interconnect and monolithic 3D demonstrate that principles behind the L2S framework are applicable for more than one configuration. Moreover, L2S-based DPM policies achieve up to 30% energy-delay product savings and reduce the peak chip temperature by up to 17 °C compared to the state-of-the-art ML methods for an allowable performance overhead of only 5%.

Techno-Economic Optimization of SOC Design and Operating Conditions in a Solid Oxide Fuel Cell-Gas Turbine Hybrid System

In a circular economy, highly efficient energy conversion systems are paramount to maximize resource utilization and minimize waste production, including carbon dioxide emissions. Solid oxide fuel cell-gas turbine hybrid systems, which can reach efficiencies of greater than 75%-LHV, have demonstrated to be a promising technology on the way to cleaner power generation. During the energy transition period, solid oxide fuel cell-gas turbine hybrid systems are likely to be operated on natural gas, however, their scalability allows these systems to reach very high efficiencies even at small scales, enabling the use of distributed resources such as biogas. In this presentation the authors will discuss key performance and economic metrics of small-scale (10 MW) advanced solid oxide fuel cell-gas turbine hybrid systems and their relation to cell design and system design elements. Current challenges in solid oxide fuel cell development include thermal cell management and production cost. This presentation presents findings of how cell design parameters influence thermal gradients and specific solid oxide cell costs on a $/kW-basis under hybrid system operating conditions. Moreover, specific cell components are identified, and effects will be discussed that can synergistically reduce thermal stress and specific cell cost at the same time. Informed by this analysis, the optimized cell design is integrated into a solid oxide fuel cell-gas turbine hybrid system in order to provide a comprehensive analysis of system operating conditions under consideration of thermal cell gradients, and new insights into economics and levelized cost of electricity are provided. The presentation will discuss the impact of fuel utilization, operating voltage, and operating pressure upon the heat integration, system’s operating window, and power output. A discussion of economic parameters will highlight cost driving factors to inform research on the next generation of solid oxide cells.

Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O

Modern SoCs contain billions of transistors, thousands of replicated cores, and are manufactured using advanced technology nodes to meet the computing requirements of applications such as AI, ML, and datacenter [1]. As the size and complexity of these SoC designs continue to increase, the effort involved in design-for-test (DFT), pattern generation, and testing has also increased dramatically. GPIO pins used for scan testing are now becoming the bottleneck in maintaining and reducing test time. The following subsections explain major challenges faced by designers when using traditional scan pins for delivering scan test data to the SoC.