Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O

Abstract

Modern SoCs contain billions of transistors, thousands of replicated cores, and are manufactured using advanced technology nodes to meet the computing requirements of applications such as AI, ML, and datacenter [1]. As the size and complexity of these SoC designs continue to increase, the effort involved in design-for-test (DFT), pattern generation, and testing has also increased dramatically. GPIO pins used for scan testing are now becoming the bottleneck in maintaining and reducing test time. The following subsections explain major challenges faced by designers when using traditional scan pins for delivering scan test data to the SoC.