Smart-cut Process Research Articles

The Study on Defects of Germanium-on-Insulator Fabricated by a Low Temperature Smart-Cut Process

Germanium-on-insulator (GeOI) was manufactured by a low temperature Smart-cut process. The blistering of H-implanted Ge wafer was first studied and the kinetics of blistering onset (time) as a function of annealing temperature was described to determine the subsequent splitting. Germanium layer transfer was achieved by a 2700C annealing after the atomic level Ge/SiO2 wafer bonding was formed by a 1500C annealing. The defects on the transferred Ge layer were mitigated thanks to the extended annealing and mainly distributed at the rim of GeOI wafer.

The Study on Defects of Germanium-on-Insulator Fabricated by a Low Temperature Smart-Cut Process

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The Annealing Kinetic Study on Germanium Surface Blistering by Hydrogen Implantation

The annealing blistering after hydrogen implantation is a fundamental to achieve GeOI (germanium-on-insulator) by the well-known Smart-cut process. The impacts of H implantation dose and energy on the annealing kinetic plots are studied. The experimental results indicated: (1) the implantation with low dose or energy results in Arrhenius plot with a break point that separate the plot into two regions due to different activation energy; (2) the situation of the kinked kinetic plot, high and low temperature corresponding to high and low activation energy, is against that for other known materials; (3) the unitary activation energy occurs as either implantation dose or energy is enhanced. Moreover, the critical size to form craters increases with the rise of either dose or energy in H-implanted Ge. The variation of the kinetic plot may be related to the different desorption energy from the diverse types of H-platelets with distinct bind energy in germanium.

Annealing of hydrogen-induced defects in RF-plasma-treated Si wafers: ex situ and in situ transmission electron microscopy studies

The smart-cut™ process is based on inducing and processing structural defects below the free surface of semiconductor wafers. The necessary defects are currently induced by implantation of light elements such as hydrogen or helium. An alternative softer way to induce shallow subsurface defects is by RF-plasma hydrogenation. To facilitate the smart-cut process, the wafers containing the induced defects need to be subjected to an appropriate thermal treatment. In our experiments, (0 0 1) Si wafers are submitted to 200 and 50 W hydrogen RF-plasma and are subsequently annealed. The samples are studied by transmission electron microscopy (TEM), before and after annealing. The plasma-introduced defects are {1 1 1} and {1 0 0} planar-like defects and nanocavities, all of them involving hydrogen. Many nanocavities are aligned into strings almost parallel to the wafer surface. The annealing is performed either by furnace thermal treatment at 550 °C, or by in situ heating in the electron microscope at 450, 650 and 800 °C during the TEM observations. The TEM microstructural studies indicate a partial healing of the planar defects and a size increase of the nanometric cavities by a coalescence process of the small neighbouring nanocavities. By annealing, the lined up nanometric voids forming chains in the as-hydrogenated sample coalesced into well-defined cracks, mostly parallel to the wafer surface.

Stress Adjustment and Bonding of H-Implanted 2 in. Freestanding GaN Wafer: The Concept of Double-Sided Splitting

Heterointegration of thin layers obtained from freestanding GaN wafers by the Smart-Cut process faces major challenges due to strong wafer bowing. The post-implantation bow was found to range between ∼40 and 60 μm for 2 in. wafers, prohibiting any bonding of H-implanted GaN. Here, we demonstrate that stress engineering by back-side implantation is an effective strategy to manipulate the bow to meet the criterion of long-range flatness. Based on our approach, high-quality bonding of a 2 in. freestanding GaN wafer onto sapphire was achieved. An efficient method to transfer thin layers from freestanding GaN is proposed.

GERMANIUM ON SAPPHIRE

This paper explores the potential of germanium on sapphire (GeOS) wafers as a universal substrate for System on a Chip (SOC), mm wave integrated circuits (MMICs) and optical imagers. Ge has a lattice constant close to that of GaAs enabling epitaxial growth. Ge , GaAs and sapphire have relatively close temperature coefficients of expansion (TCE), enabling them to be combined without stress problems. Sapphire is transparent over the range 0.17 to 5.5 μm and has a very low loss tangent (α) for frequencies up to 72 GHz. Ge bonding to sapphire substrates has been investigated with regard to micro-voids and electrical quality of the Ge back interface. The advantages of a sapphire substrate for integrated inductors, coplanar waveguides and crosstalk suppression are also highlighted. MOS transistors have been fabricated on GeOS substrates, produced by the Smart-cut process, to illustrate the compatibility of the substrate with device processing.

Fracture mechanics analysis on Smart-Cut® technology. Part 2: Effect of bonding flaws

In Part 2 of the paper on the Smart-Cut process, the effects of bonding flaws characterized by the size and internal pressure before and after splitting are studied by using fracture mechanics models. It is found that the bonding flaws with large size are prone to cause severe deviation of defect growth, leading to a non-transferred area of thin layer when splitting. In a practical Smart-Cut process where the internal pressure of bonding flaws is very small, large interfacial defects always promote defect growth in the splitting process. Meanwhile, increasing the internal pressure of the bonding flaws decreases the defect growth and its deviation before splitting. The mechanism of relaxation of stiffener constraint is proposed to clarify the effect of bonding flaws. Moreover, the progress of the splitting process is analyzed when bonding flaws are present. After splitting, those bonding flaws with large size and high internal pressure are vulnerable for the blistering of the thin film during high-temperature annealing.

Fracture mechanics analysis on Smart-Cut® technology. Part 1: Effects of stiffening wafer and defect interaction

In the present paper, continuum fracture mechanics is used to analyze the Smart-Cut process, a recently established ion cut technology which enables highly efficient fabrication of various silicon-on-insulator (SOI) wafers of high uniformity in thickness. Using integral transform and Cauchy singular integral equation methods, the mode-I and mode-II stress intensity factors, energy release rate, and crack opening displacements are derived in order to examine several important fracture mechanisms involved in the Smart-Cut process. The effects of defect interaction and stiffening wafer on defect growth are investigated. The numerical results indicate that a stiffener/handle wafer can effectively prevent the donor wafer from blistering and exfoliation, but it slows down the defect growth by decreasing the magnitudes of SIF’s. Defect interaction also plays an important role in the splitting process of SOI wafers, but its contribution depends strongly on the size, interval and internal pressure of defects. Finally, an analytical formula is derived to estimate the implantation dose required for splitting a SOI wafer.

Fracture mechanics analysis of the effects of temperature and material mismatch on the Smart-Cut ® technology

Annealing temperature is very critical in the Smart-Cut process especially when material mismatch exists. Experiments have shown that high temperature along with thermal mismatch may fail the Smart-Cut process by inducing severe deformation or cracks on the films. The present paper, following our previous investigations on the Smart-Cut process, studies the effects of temperature and material mismatch on wafer splitting in the Smart-Cut technology by using fracture mechanics analysis. The influence of temperature is explored through its effect on the internal pressure inside the defects and thermal stresses whether the donor wafer and the handle wafer are the same materials or not. Our analysis shows that increasing temperature may promote defect growth by increasing the internal pressure, and that thermal stresses arising from temperature change accompanied by material mismatch may inhibit defect growth and lead to growth deviation. In addition, the results indicate that the elastic mismatch of materials plays a significant role in wafer splitting in the Smart-Cut process even when the thermal stresses vanish.

Characterization of bonded silicon-on-aluminum-nitride wafers with RBS, TEM and HRXRD techniques

Bonded silicon-on-insulator (SOI) materials via the Smart-cut TM (or ion-cut) process attract increasing interests due to their great capability and versatility in fabricating novel virtual substrates. Previously we reported the successful fabrication of silicon-on-aluminum-nitride (SOAN) structure with smart-cut process [C.L. Men, Z. Xu, Z. An, X.Y. Xie, M. Zhang, C.L. Lin, Physica B 324 (2002) 229]. In this work, we characterize the bonded SOAN structure with Rutherford backscattering spectroscopy (RBS), transmission electron microscopy (TEM) together with Kikuchi line diffraction patterns, and high resolution X-ray diffraction (HRXRD) techniques. It is found that, after smart-cut process, the top Si layer preserves a rather good single crystalline quality, while strain is induced in top Si and can be altered in the annealing step. The rotational misalignment during bonding step can be evaluated by Kikuchi line patterns. Our discussions here may be common for all bonded virtual substrates via smart-cut technology.

Fracture Mechanics Analysis on Smart-Cut® Technology: Effects of Stiffening Wafer and Defect Interaction

In the present paper, continuum fracture mechanics is used to analyze the Smart-Cut process, a recently established ion cut technology which enables highly efficient fabrication of various silicon-on-insulator (SOI) wafers of very high uniformity in thickness. Using integral transform and Cauchy singular integral equation methods, the mode-I and mode-II stress intensity factors, energy release rate and crack opening displacements are derived in order to examine several important fracture mechanisms involved in the Smart-Cut process. The effects of defect interaction and stiffening wafer on defect growth are investigated. The numerical results indicate that a stiffener/handle wafer can effectively prevent the donor wafer from blistering and exfoliation, but it slows down the defect growth by decreasing the magnitudes of SIFs. Defect interaction also plays an important role in the splitting process of SOI wafers, but its contribution depends strongly on the size, interval and internal pressure of defects. Finally, an analytical formula is derived to estimate the implantation dose required for splitting a SOI wafer.

Compressive uniaxially strained silicon on insulator by prestrained wafer bonding and layer transfer

Wafer level compressive uniaxially strained silicon on insulator is obtained by direct wafer bonding of silicon wafers in cylindrically curved state, followed by thinning one of the wafers using the smart-cut process. The mapping of the wafer bow demonstrates the uniaxial character of the strain induced by the cylindrical bending. The interfacial properties are investigated by infrared transmission imaging, scanning acoustic microscopy, and transmission electron microscopy. UV-Raman spectroscopy is employed to determine the strain in the thin transferred layer as a function of radius of curvature of the initial bending.

Uniaxially strained silicon by wafer bonding and layer transfer

Uniaxial strain on wafer-level was realised by mechanically bending and direct wafer bonding of Si wafers in the bent state followed by thinning one of the Si wafers by the smart-cut process. This approach is flexible and allows to obtain different strain values at wafer-level in both tension and compression. UV micro-Raman spectroscopy was used to determine the strain in the thin transferred Si layers. Numerical modelling by 3D finite elements of the strain provided a good description of the experimental results.

Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro/Nanoelectronics

Wafer direct bonding refers to the process of adhesion of two flat mirror-polished wafers without using any intermediate gluing layers in ambient air or vacuum at room temperature. The adhesion of the two wafers occurs due to attractive long range van der Waals or hydrogen bonding forces. At room temperature the bonding energy of the interface is low and higher temperature annealing of the bonded wafer pairs has to be carried out to enhance the bonding energy. In this paper, we describe the prerequisites for the wafer-bonding process to occur and the methods to prepare the suitable surfaces for wafer bonding. The characterization techniques to assess the quality of the bonded interfaces and to measure the bonding energy are presented. Next, the applications of wafer direct bonding in the fabrication of novel engineered substrates such as silicon-on-insulator and other on-insulator substrates are detailed. These novel substrates, often called hybrid substrates, are fabricated using wafer bonding and layer splitting via a high dose hydrogen/helium implantation and subsequent annealing. The specifics of this process, also known as the smart-cut process, are introduced. Finally, the role of wafer bonding in future nanotechnology applications such as nanotransistor fabrication, three-dimensional integration for high-performance micro/nanoelectronics, nanotemplates based on twist bonding, and nano-electro-mechanical systems is discussed

From Smart-Cut to Soft-Cut: Mechanisms of Hydrogen Plasma Supported Layer Exfoliation in Silicon

Comparative investigations of silicon layer exfoliation within the Smart-Cut process and its progression at lower H+ implantation doses and subsequent H-plasma exposure (Soft-Cut) were done by µ-Raman spectroscopy, scanning electron microscopy (SEM) and atomic force microscopy (AFM) on (100)-oriented Cz Si wafers. Blister formation and evolution at various process temperatures were analyzed to clarify the mechanisms of layer exfoliation for both approaches. On base of the Raman analyses and supporting SEM and AFM measurements of samples prepared under various process temperatures, we identified the V2H6 defect complexes as the precursor of blisters for the Smart-Cut scenario. Under Soft-Cut conditions (100)-oriented platelets created during H-plasma exposure can be identified as the prevailing precursors of blisters.

Buckling characteristics of SiGe layers on viscous oxide

Buckled SiGe films on viscous oxide with different Ge content are studied by wafer bonding and smart-cut process. Compressively strained SiGe layers on the viscous oxide were relaxed to form the buckled state after thermal treatment. Two-dimensional buckling on blanket films is observed. A higher Ge concentration results in a smaller buckling amplitude and a smaller buckling period. Both buckling amplitude and period increase as oxidation time is increased. A small SiGe film (mesa) area can inhibit buckling. Semiempirical analysis gives the critical area size, below which no buckling is observed in the equilibrium states. The critical area size decreases with increasing Ge concentration and decreasing thickness of SiGe films.

Ultrathin Strained-SOI by Stress Balance on Compliant Substrates and FET Performance

Ultrathin, strained-silicon-on-insulator (s-SOI) structures without a residual silicon-germanium (SiGe) underlayer have been fabricated using stress balance of bi-layer structures on compliant borophosphorosilicate glass (BPSG). The bi-layer structure consisted of SiGe and silicon films, which were initially pseudomorphically grown on a silicon substrate and then transferred onto BPSG by a wafer bonding and SmartCut process. The viscous flow of the BPSG during a high-temperature anneal then allowed the SiGe/Si bi-layer to laterally coherently expand to reach stress balance, creating tensile strain in the silicon film. No dislocations are required for the process, making it a promising approach for achieving high-quality strained-silicon for device applications. To prevent the diffusion of boron and phosphorus into the silicon from the BPSG, a thin nitride film was inserted between the bi-layer and BPSG to act as a diffusion barrier, so that a lightly doped, sub-10-nm s-SOI layer (0.73% strain) was demonstrated. N-channel MOSFETs fabricated in a 25-nm silicon layer with 0.6% strain showed a mobility enhancement of 50%.

The influence of the ion implantation temperature and the dose rate on smart-cut© in GaAs

The temperature and dose rate dependence of the smart-cut© process in GaAs have been investigated in this paper. The distribution of hydrogen and the implantation damage in the samples were studied by ion beam analysis and X-ray diffraction. It was found that at higher temperatures, hydrogen is mobile in the lattice and can rearrange into the platelets, microcracks and bubbles which are present in blistered material, thus relieving the strain in the lattice. The dose rate was also found to be significant for the smart-cut process, as blistering and exfoliation are inhibited at low dose rates.

The influence of the ion implantation temperature and the flux on smart-cut© in GaAs

The dependence of hydrogen flux and substrate temperature during implantation on the smart-cut© process in GaAs have been investigated in this paper. The lattice disorder in the samples was studied by ion beam analysis. It was found that both the flux and the implant temperature are significant for the smart-cut process. As the flux increases, the degree of exfoliation and the mean blister size increases, while the number density of blisters falls, indicating that blister evolution is enhanced at high dose rates.

Characterization and field-emission property of aligned porous carbon nanotube film by hydrogen-ion implantation

To enhance the field emission of carbon nanotube (CNT) films, a novel technique that combines hydrogen-ion implantation used in the silicon-on-insulation smart-cut process and plasma-enhanced chemical vapor deposition was developed to produce an aligned porous carbon nanotube (AP-CNT) film on a Si substrate. All steps in the AP-CNT synthesis were carried out in vacuum, which reduced possible contamination. The morphology and the field-emission properties of the CNT films were investigated and results show that CNT holes with a diameter of 5 μm and a depth of 30 μm were produced in the AP-CNT film. The alignment of the CNTs is visibly improved. Due to the implantation treatment, the turn-on field of the CNT films decreased from 1.5 to 0.8 V/μm, and the emission-current (and dot) density obviously increased. This field-emission improvement may mainly arise from the holes formed in the AP-CNT films. The edges of these holes not only intensified the electron emission but also increase the emission site density of the CNT films.