Small Hardware Research Articles

General Hardware, Inc.

The owners of a chain of hardware stores are preparing the most recent quarter financial statements. A number of business details are provided, including information to assess accrual accounting net income: sales, cost of sales, operating expenses, interest, depreciation, and taxes. The most recent balance sheet is provided, enabling an assessment of basic accruals (e.g., tax payable). This case may be used as a stand-alone exercise to illustrate the preparation of balance sheets and income statements using transactions and accruals. Excerpt UVA-C-2446 Dec. 16, 2020 General Hardware, Inc. Ginny and Joe Miller opened a small hardware store in 2004, using their own cash savings and borrowing a small sum from Ginny's parents. Nothing gave them more pride than owning and operating a locally owned business, even if it was complicated by the constant pressures placed on them by big-box retailers. But by 2019, business was booming. General Hardware had five locations, and the Millers were considering an even greater expansion in the coming year, perhaps offering their own version of a national franchise model. The drop-off in activity during the first quarter of 2020, however, dampened those plans. The quarter turned out to be a time for retrenchment and planning for a sustained period of contraction. The following is a summary of first quarter activity for the year 2020, along with the final December 31, 2019, balance sheet (see Exhibit1). · Product sales totaled $ 3 million (all customers paid with cash), and the company had paid $ 2.2million for that inventory sold. . . .

A Test Response Compression Method for Monolithic 3-D ICs Based on 3-D Haar Wavelet Transforms

This article presents an advanced method for monolithic 3-D integrated circuits (ICs)’ test compression based on 3-D Haar wavelet transforms. The main purpose of this study is to reduce the test response data consumption while achieving higher fault coverage using new Haar wavelet transforms. Considering the faultiness of test compression, this article would like to introduce the “3-D Haar wavelet transforms,” which would update part of 2-D butterfly unit into 3-D butterfly unit based on the traditional Haar wavelet transforms to simplify the test response output nodes. To better achieve the purpose, a new no-X-unknown-carry adder is applied to build 3-D no-X-unknown-carry Haar wavelet transform (3-D_NxUC_HWT), which not only could solve X-masking but also could transmit an X-bit efficiently to make a delay fault diagnosis. In addition, the constructed reuse architecture makes it possible to plan reasonably the test compression structure by making full use of monolithic interlayer vias to shorten the parallel transmission length. In this study, the test point data are output to the test compressor in parallel through interlayer vias and the compressed results are shifted out by serial scan chain to shorten the test time. The experimental results clearly demonstrate that this method has superiority of higher test coverage, faster test time, fewer test analysis data, and smaller hardware overhead.

A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

A continuous-rate referenceless clock and data recovery (CDR) circuit with an unlimited frequency acquisition capability is presented. The proposed frequency detector (FD) is derived from a multi-phase oversampling FD. Through accurate analysis of the root causes limiting the capture range, the extension techniques are proposed and digitally implemented by a small hardware overhead. The FD achieves the unlimited frequency detection capability and exhibits robust operation regardless of the initial clock frequency. The effect of the quadrature error is analyzed and verified by simulation. In addition, a frequency lock detector is implemented to control the loop gain for fast frequency acquisition. The prototype CDR circuit was designed and fabricated in a 65-nm CMOS process, occupying an active area of 0.045 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The CDR circuit achieves a capture range from 4 Gb/s to 20 Gb/s, which is limited only by the oscillator operating range. The worst case acquisition time is 25 μs with a PRBS31 pattern. The CDR circuit achieves a BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and an energy efficiency of 1.87 pJ/b.

Fast and accurate detection of kiwifruit in orchard using improved YOLOv3-tiny model

Automatic detection of kiwifruit in the orchard is challenging because illumination varies through the day and night and because of color similarity between kiwifruit and the complex background of leaves, branches and stems. Also, kiwifruits grow in clusters, which may result in having occluded and touching fruits. A fast and accurate object detection algorithm was developed to automatically detect kiwifruits in the orchard by improving the YOLOv3-tiny model. Based on the characteristics of kiwifruit images, two convolutional kernels of 3 × 3 and 1 × 1 were added to the fifth and sixth convolution layers of the YOLOv3-tiny model, respectively, to develop a deep YOLOv3-tiny (DY3TNet) model. It takes multiple 1 × 1 convolutional layers in intermediate layers of the network to reduce the computational complexity. Testing images captured from day and night and comparing with other deep learning models, namely, Faster R-CNN with ZFNet, Faster R-CNN with VGG16, YOLOv2 and YOLOv3-tiny, the DY3TNet model achieved the highest average precision of 0.9005 with the smallest data weight of 27 MB. Furthermore, it took only 34 ms on average to process an image of a resolution of 2352 × 1568 pixels. The DY3TNet model, along with the YOLOv3-tiny model, showed better performance on images captured with flash than those without. Moreover, the experiments indicated that the image augmentation process could improve the detection performance, and a simple lighting arrangement could improve the success rate of detection in the orchard. The experimental results demonstrated that the improved DY3TNet model is small and efficient and that it would increase the applicability of real-time kiwifruit detection in the orchard even when small hardware devices are used.

Achieving reliable UDP transmission at 10 Gb/s using BSD socket for data acquisition systems

User Datagram Protocol (UDP) is a commonly used protocol for data transmission in small embedded systems. UDP as such is unreliable and packet losses can occur. The achievable data rates can suffer if optimal packet sizes are not used. The alternative, Transmission Control Protocol (TCP) guarantees the ordered delivery of data and automatically adjusts transmission to match the capability of the transmission link. Nevertheless UDP is often favored over TCP due to its simplicity, small memory and instruction footprints. Both UDP and TCP are implemented in all larger operating systems and commercial embedded frameworks. In addition UDP also supported on a variety of small hardware platforms such as Digital Signal Processors (DSP) Field Programmable Gate Arrays (FPGA). This is not so common for TCP. This paper describes how high speed UDP based data transmission with very low packet error ratios was achieved. The near-reliable communications link is used in a data acquisition (DAQ) system for the next generation of extremely intense neutron source, European Spallation Source. This paper presents measurements of UDP performance and reliability as achieved by employing several optimizations. The measurements were performed on Xeon E5 based CentOS (Linux) servers. The measured data rates are very close to the 10 Gb/s line rate, and zero packet loss was achieved. The performance was obtained utilizing a single processor core as transmitter and a single core as receiver. The results show that support for transmitting large data packets is a key parameter for good performance. Optimizations for throughput are: MTU, packet sizes, tuning Linux kernel parameters, thread affinity, core locality and efficient timers.

Real-Time Controller Design Test Bench for High-Voltage Direct Current Modular Multilevel Converters

Modular multilevel converters (MMCs), with their inherent features and advantages over other conventional converters, have gained popularity and remain an ongoing topic of research. Many scholars have solved issues related to the operation, control, protection, and reliability of MMCs using simulation software and small hardware prototypes. We propose a novel approach for an MMC controller design with real-time systems. By utilizing a key benefit of LabVIEW Multisim co-simulation, an MMC control algorithm that can be deployed on a field-programmable gate array (FPGA) was developed in LabVIEW. The complete circuit was designed in Multisim, and a co-simulation was performed to drive an MMC model. The benefit of this topology is that control algorithms can be designed in a LabVIEW FPGA and tested with the Multisim co-simulation circuit to obtain simulation results. Once the controller works and provides satisfactory results, the same algorithm can be deployed in any NI (National Instruments) FPGA-based controller, like a compact remote input/output (RIO), to control real-time MMCs designed in an NI PCI eXtensions for Instrumentation (PXI) system. This method saves time and provides flexibility for effectively designing control algorithms and implementing them in an FPGA for real-time model implementation.

Area-Efficient Differential Fault Tolerance Encoding for Finite State Machines

A differential fault tolerance encoding is presented for finite state machines (FSMs) to improve their area efficiency. As the manufacturing technology for semiconductors continues to scale down, the probability of the occurrence of unexpected faults in integrated circuits has been increasing. Because an FSM controls an entire digital circuit, the faults in FSMs should be carefully addressed. Whereas the previous encoding applies a fault tolerance scheme to all the states in an FSM, the proposed encoding applies a fault tolerance scheme to only specific states depending on their importance. Compared with the previous complete fault tolerance encoding, the proposed encoding provides a comparable failure probability with a small hardware by applying the fault tolerance scheme differently to each state. The proposed method improves the area efficiency by 36.1%, 43.8%, 49.2%, and 74.6% compared with that by the non-fault tolerance, previous hardware redundancy, information redundancy, and time redundancy methods, respectively. Consequently, the proposed method can provide a flexible solution by applying the fault tolerance differently depending on the importance of the states.

Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel

Stochastic computing (SC) in recent years has been defined as a digital computation approach that operates on streams of random bits that represent probability values. SC can perform complex tasks with much smaller hardware footprints compared with conventional binary methods, but previous methods on SC circuits operated on serial bit streams, which leads to high-latency implementations. This article presents a significant improvement over previous work; it provides a deterministic parallel bit shuffling network that can use a simple deterministic thermometer encoding of data, resulting in zero random fluctuation and high accuracy, yet keeping the output bit-stream length constant. We use core “stochastic” logic circuits that do not employ constant coefficients, making them significantly smaller than traditional stochastic logic that use a significant amount of resources to generate such coefficients. Our experiments show that compared with previous SC methods, our method has up to $3\times $ smaller mean absolute error, and better area $\times $ delay and power efficiency. Compared with conventional binary methods, our method is better in terms of area $\times $ delay at 8-bit resolution. It shows better power efficiency ( $40\times $ , $18\times $ , and $8\times $ Gops/W at 8-, 10-, and 12-bit resolutions) compared with conventional binary.

MIoT: Metamorphic IoT Platform for On-Demand Hardware Replacement in Large-Scaled IoT Applications.

As the Internet of Things (IoT) is becoming more pervasive in our daily lives, the number of devices that connect to IoT edges and data generated at the edges are rapidly increasing. On account of the bottlenecks in servers, due to the increase in data, as well as security and privacy issues, the IoT paradigm has shifted from cloud computing to edge computing. Pursuant to this trend, embedded devices require complex computation capabilities. However, due to various constraints, edge devices cannot equip enough hardware to process data, so the flexibility of operation is reduced, because of the limitations of fixed hardware functions, relative to cloud computing. Recently, as application fields and collected data types diversify, and, in particular, applications requiring complex computation such as artificial intelligence (AI) and signal processing are applied to edges, flexible processing and computation capabilities based on hardware acceleration are required. In this paper, to meet these needs, we propose a new IoT platform, called a metamorphic IoT (mIoT) platform, which can various hardware acceleration with limited hardware platform resources, through on-demand transmission and reconfiguration of required hardware at edges instead of via transference of sensing data to a server. The proposed platform reconfigures the edge’s hardware with minimal overhead, based on a probabilistic value, known as callability. The mIoT consists of reconfigurable edge devices based on RISC-V architecture and a server that manages the reconfiguration of edge devices based on callability. Through various experimental results, we confirmed that the callability-based mIoT platform can provide the hardware required by the edge device in real time. In addition, by performing various functions with small hardware, power consumption, which is a major constraint of IoT, can be reduced.

A multiple linear regression model approach for two-class fNIR data classification

Functional near-infrared (fNIR)-based motor imagery (MI) classification is an interesting challenge for the brain–computer interface (BCI) implementation. The success of the fNIR-BCI mostly depends on the classification performance. Usually, machine learning-based complex algorithms are used to classify the fNIR-MI data which often proves impractical to program in small hardware. Therefore, the practical small and low price hardware-based BCI system demands simple algorithm that can provide satisfactory classification accuracy. This paper proposes an fNIR-MI data classifier utilizing the multiple linear regression model (MLRM). In this work, two-class fNIR-MI data were acquired for feature extraction and classification. The predictive model for classification was prepared by the proposed method. Additionally, the same dataset was classified by the widely used classification method—support vector machine (SVM) and linear discriminant analysis (LDA). The results reveal that the proposed multiple linear regression model-based classifier (MLRMC) shows almost equivalent results compared to the SVM and LDA on the same features, although MLRM is a much simpler algorithm than that of the others. Therefore, the outcomes of this research work claim that the proposed MLRMC is a good choice as a classifier for fNIR-like simple signal classification.

IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes

Silent Data Corruptions (SDCs), those errors that escape detection methods, are critical for system designers because they may result in systems failures. In order to catch SDCs, mechanisms should focus on the behavioural aspects of errors in addition to their physical location or error patterns. Therefore, protection codes like parity, hamming, and the Reed-Solomon code, which heavily depend on the physical location of data bits, are not enough in processors for detection of computing errors. Using characterizing data behaviour during program executions, we have observed value locality in results of destination register for each instruction binary code (instruction opcode and operand codes). This locality exists not only in the results of each instruction, but also in the results of instructions at different memory locations having the same binary code. As a result, an architecture called Instruction Result History Table (IRHT) is presented, which is indexed by the instruction binary code. In the IRHT, a history of values produced by the same instruction binary codes are stored in and utilized during each instruction execution cycle. Any mismatch between the stored values in the IRHT and those generated by current execution, indicates an SDC syndrome. To confirm having SDCs with a high level of confidence, a second execution of the current instruction is issued. A duplication of the execution confirms whether SDC occurred. In the case of SDCs, a third instruction execution with the help of a majority voting frees the system of SDC. Several extensive simulations showed that, up to 83.54% of SDCs are detectable with the help of this locality. Moreover, with the small hardware, IRHT, i.e., 16 kB size, 80.66% of SDCs can be detected on average. Note that the presented method can detect those errors that escape conventional detection mechanisms. So, it can be utilized in conjunction with other conventional methods.

A Low Complexity Joint Encryption-Modulation Method for IoT Sensor Transceivers

Physical layer encryption (PLE) is a new research trend for securing data in communication systems. However, conventional procedures in works on PLE are of high complexity and degrade the packet error rate (PER) performance of the system. They are therefore not yet suitable for IoT sensors’ transceiver, which has limited power and computational resource. In this paper, we propose a low complexity PLE method named as joint encryption-modulation (JEM) for small transceivers such as IoT sensors. In our JEM method, data is encrypted after modulation to preserve high security. Our JEM method does not make change the constellation of the modulation after encryption; therefore, the encryption does not degrade PER performance of the system as the conventional works do. Furthermore, the encryption is performed by XOR gates and multiplexers only. It is, therefore, low complexity. Our experiment results show that the JEM method improves about 3 dB of PER performance as compared with that of conventional works. JEM method can support multiple modulation types such as BPSK, QPSK, 16-256 QAM within a small hardware cost. Compared with conventional works, JEM’s hardware resource is reduced by 87.5% in terms of FPGA synthesis and 86.5% in terms of the ASIC circuit. ASIC static power consumption of JEM is reduced by 80.6%.

New RSA Encryption Mechanism Using One-Time Encryption Keys and Unpredictable Bio-Signal for Wireless Communication Devices

Applying the data encryption method used in conventional personal computers (PC) to wireless communication devices such as IoT is not trivial. Because IoT equipment is extremely slow in transferring data and has a small hardware area compared with PCs, it is difficult to transfer large data and perform complicated operations. In particular, it is difficult to apply the RSA encryption method to wireless communication devices because it guarantees the stability of data encryption because it is difficult to factor extremely large prime numbers. Furthermore, it has become even more difficult to apply the RSA encryption method to IoT devices as a paper recently published indicated that it enables rapid fractional decomposition when using RSA encryption with a prime number generated through several pseudo-random number generators. To compensate for the disadvantages of RSA encryption, we propose a method that significantly reduces the encryption key using a true prime random number generator (TPRNG), which generates a prime number that cannot be predicted through bio-signals, and a disposable RSA encryption key. TPRNG has been verified by the National Institute of Standards and Technology. The NIST test and an RSA algorithm are implemented through Verilog.

Area-Efficient Error Detection Structure for Linear Feedback Shift Registers

This paper presents a novel error detection linear feedback shift register (ED-LFSR), which can be used to realize error detection with a small hardware overhead for various applications such as error-correction codes, encryption algorithms and pseudo-random number generation. Although the traditional redundancy methods allow the incorporation of the error detection/correction capability in the original LFSRs, they suffer from a considerable amount of hardware overheads. The proposed ED-LFSR alleviates such problems by employing the parity check technique. The experimental results indicate that the proposed ED-LFSR requires an additional area of only 31.1% compared to that required by the conventional LFSR and it saves 39.1% and 31.9% of the resources compared to the corresponding utilization of the hardware and time redundancy methods.

On-the-fly Page Migration and Address Reconciliation for Heterogeneous Memory Systems

For efficient placement of data in flat-address heterogeneous memory systems consisting of fast (e.g., 3D-DRAM) and slow memories (e.g., NVM), we present a hardware-based page migration technique. Unlike epoch-based approaches that migrate heavily accessed (“hot”) pages from slow to fast memories at each epoch interval, we migrate a page immediately when it becomes hot (“on-the-fly”), using hardware in user-transparent manner and with minimal OS intervention. The management of physical addresses due to page relocation becomes cumbersome and requires costly OS intervention. We use a small hardware remap table to keep track of new physical addresses of the migrated pages. This limits address reconciliation to occur only at periodic evictions of old remap entries. Also, we propose a hardware-orchestrated light-weight address reconciliation process. For our studied heterogeneous memory system, on-the-fly page migration with hardware-assisted address reconciliation provides 74% and 24% IPC improvements, on average for a set of SPEC CPU2006 workloads when compared to a baseline without any page migration and a system with on-the-fly page migration using OS-based address reconciliation, respectively. Furthermore, we present an analytical model for classifying applications as page migration friendly (applications that show performance gains from page migration) or unfriendly based on memory access behavior.

Implementation and Statistical Tests of a Block Cipher Algorithm MISTY1*

With the development of communication network and new information technologies, the volume of data exchanged is growing, particularly with the of IoTs. There security has become a major concern, especially in sensitive activities. Such security requirements call for efficient cryptographic encryption algorithms, with a small hardware footprint. The current trend is towards light cryptographic algorithms (lightweight). These are designed for power systems with limited storage capacity. This paper proposes the study, hardware implementation and statistical test of block cipher algorithm MISTY1. Its optimized version for a hardware implementation is known as KASUMI, used in the context of 3GPP compliant mobile networks, including 2G (GSM) and 3G (UMTS).

Efficient Pipelined Broadcast with Monitoring Processing Node Status on a Multi-Core Processor

This paper presents an efficient pipelined broadcasting algorithm with the inter-node transmission order change technique considering the communication status of processing nodes. The proposed method changes the transmission order for the broadcast operation based on the communication status of processing nodes. When a broadcast operation is received, a local bus checks the remaining pre-existing transmission data size of each processing node; it then transmits data according to the changed transmission order using the status information. Therefore, the synchronization time can be hidden for the remaining time, until the pre-existing data transmissions finish; as a result, the overall broadcast completion time is reduced. The simulation results indicated that the speed-up ratio of the proposed algorithm was up to 1.423, compared to that of the previous algorithm. To demonstrate physical implementation feasibility, the message passing engine (MPE) with the proposed broadcast algorithm was designed by using Verilog-HDL, which supports four processing nodes. The logic synthesis results with TSMC 0.18 μm process cell libraries show that the logic area of the proposed MPE is 2288.1 equivalent NAND gates, which is approximately 2.1% of the entire chip area. Therefore, performance improvement in multi-core processors is expected with a small hardware area overhead.

Research and Implementation of Channel Estimation Algorithm Based on Wideband Micro-power System

Channel estimation and equalization are the keys to realize wideband micro-power wireless communication system. In this paper, the channel estimation algorithm is improved according to the frame structure characteristics of wideband micro-power. Compared with the original algorithm, new algorithm is more suitable for this system and its performance is improved by 0.2dB. By establishing the system simulation model in MATLAB environment, the corresponding channel estimation algorithm is used to simulate and compare. The performance of the improved algorithm is verified and the improved algorithm is implemented on the FPGA platform. In the process of hardware implementation, formula transformation is used to reduce the use of multipliers in complex multiplication and reduce resource consumption. The results of ISE Design Suite 14.7 synthesis and Modelsim simulation show that the algorithm has low algorithm complexity, small hardware resources, and the estimation accuracy meets the expectations and meets the application requirements.

A Novel Four-in-One Variable Frequency Drive Topology

Of late, most types of ac motors can be operated using variable frequency drives (VFDs) by merely selecting the type of motor and the corresponding control method using a sophisticated all-in-one software platform. As technology improves, the VFD is becoming more of a plug and play, software-based electrical equipment. There have been no comparable technological advancement/improvements in the hardware realm except for the potential use of wide band gap devices (SiC or GaN) to reduce losses. The idea being proposed here is a hardware platform that is similar to an all-in-one software platform. By reconfiguring the hardware platform, one could achieve totally new or additional features that can enhance the overall performance of a VFD. It is shown that by adding one small hardware device as part of the main VFD, the unit can be reconfigured to provide four distinct features/functions as desired. An off-the-shelf VFD is used as an example to illustrate the various configurations achievable based on the proposed hardware modification. The proposed topology's cost, size, and features are compared with a traditional VFD with externally added components to achieve similar features/functions. In addition, the amount of time estimated to be saved in developing the proposed four-in-one converter compared to developing individual, external units to achieve similar features and functions is also investigated.

Implementation of Low density Parity Check system using Probabilistic Gradient Descent Bit Flipping Decoder

This paper represents the concept of hard decision decoder in which PGDBF is suitable decoder for the basic model of hard-choice decoder as long as low-density parity check code (LDPC) which is increase the error correction. This design introduced dynamic architecture which reduce the capability of random disarrangement of the PGDBF. The design is working on the Short Random Sequence (SRS) that is replica cover on the PGDBF decoding guidelines. In each iteration flipping number of bits these are focusing on improvement in performance and decoding delay. The best SRS is essential to manage the well-known decoding achievement of PGDBF, we introduced two kind of access with same hardware categories, but various LDPC codes are perform different behaviors. In this design we are modifying small hardware decoding unit for obtaining a good decoding explanation for present and further purpose.