A Test Response Compression Method for Monolithic 3-D ICs Based on 3-D Haar Wavelet Transforms

Abstract

This article presents an advanced method for monolithic 3-D integrated circuits (ICs)’ test compression based on 3-D Haar wavelet transforms. The main purpose of this study is to reduce the test response data consumption while achieving higher fault coverage using new Haar wavelet transforms. Considering the faultiness of test compression, this article would like to introduce the “3-D Haar wavelet transforms,” which would update part of 2-D butterfly unit into 3-D butterfly unit based on the traditional Haar wavelet transforms to simplify the test response output nodes. To better achieve the purpose, a new no-X-unknown-carry adder is applied to build 3-D no-X-unknown-carry Haar wavelet transform (3-D_NxUC_HWT), which not only could solve X-masking but also could transmit an X-bit efficiently to make a delay fault diagnosis. In addition, the constructed reuse architecture makes it possible to plan reasonably the test compression structure by making full use of monolithic interlayer vias to shorten the parallel transmission length. In this study, the test point data are output to the test compressor in parallel through interlayer vias and the compressed results are shifted out by serial scan chain to shorten the test time. The experimental results clearly demonstrate that this method has superiority of higher test coverage, faster test time, fewer test analysis data, and smaller hardware overhead.