Small Chip Size Research Articles

Estimation of power and delay in CMOS circuits using LCT

<p>With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors(HTLCT). In this paper, we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The estimation of power and delay will be discussed using LCT’s and HTLCT’s</p>

6–18 GHz GaAs pHEMT Broadband Power Amplifier Based on Dual-Frequency Selective Impedance Matching Technique

This paper presents a broadband gallium-arsenide pseudomorphic high-electron-mobilitytransistor (GaAs pHEMT) power amplifier integrated circuit (PAIC) based on a dual-frequency selective impedance matching technique for warfare applications. For a broadband PA design, lower and upper-frequency corners where serious performance degradation is likely to occur should be carefully considered. Feedback and resistive biasing circuits were adopted for driver and main stages to making their frequency responses as flat as possible. Optimum impedances of not only extended lower and upper-frequency corners but also center frequency, were then extracted. Such dual-frequency selective impedance matching technique was applied for extended lower and upper-frequency corners while checking the mismatch level for the center frequency. The proposed broadband PAIC for frequency band from 6 to 18 GHz was designed using a 0.15 μm GaAs enhanced-mode pHEMT (E-pHEMT) process. The implemented broadband PAIC with a simple two-stage structure had a very small chip size of 1.19×0.82 mm 2 . It exhibited a power gain of more than 16.4 dB and output power of 19.2 dBm. Very flat characteristics in power gain and an output power within ±1.0 dB through the whole band were achieved.

Development of Power Consumption Models for ESP8266-Enabled Low-Cost IoT Monitoring Nodes

The development of energy and cost efficient IoT nodes is very important for the successful deployment of IoT solutions across various application domains. This paper presents energy models, which will enable the estimation of battery life, for both time-based and event-based low-cost IoT monitoring nodes. These nodes are based on the low-cost ESP8266 (ESP) modules which integrate both transceiver and microcontroller on a single small-size chip and only cost about $2. The active/sleep energy saving approach was used in the design of the IoT monitoring nodes because the power consumption of ESP modules is relatively high and often impacts negatively on the cost of operating the nodes. A low energy application layer protocol, that is, Message Queue Telemetry Transport (MQTT) was also employed for energy efficient wireless data transport. The finite automata theory was used to model the various states and behavior of the ESP modules used in IoT monitoring applications. The applicability of the models presented was tested in real life application scenarios and results are presented. In a temperature and humidity monitoring node, for example, the model shows a significant reduction in average current consumption from 70.89 mA to 0.58 mA for sleep durations of 0 and 30 minutes, respectively. The battery life of batteries rated in mAh can therefore be easily calculated from the current consumption figures.

Estimation of Power and Delay in CMOS Circuits using Leakage Control Transistor

Abstract With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the introduction of new Integrated Circuit (IC) technology, the speed of the circuits has been increased by around 30%. But it was observed that for every two years, the power dissipation of a circuit doubles. The main reason for this power dissipation is leakage currents in the circuit. To reduce these leakage currents, we can reduce the width of the device. In addition to this, we can use lector techniques that use Leakage Control Transistors (LCT) and High Threshold Leakage Control Transistors (HTLCT).In this paper; we present a circuit technique that uses 130 nano-meter CMOS VLSI circuits that use two extra transistors to mitigate the leakage currents. The proposed technique overcomes the limitations posed by the existing methods for leakage reductions an average leakage reductions is 82.5%.The estimation of power and delay will be discussed using LCT’s and HTLCT’s.

Design and implementation of 75~110 GHz elliptical dual balun in 90 nm CMOS for W-Band transceiver

ABSTRACTWe demonstrate an elliptical dual balun structure for 94 GHz image radar transceiver. The results of two prototypes with small chip size of 0.0256 mm2 are reported. For the first one (i.e. dual balun 1), the input couple-line width is 4 mm and coupled-line space is 2 µm. That is, the distance between the output couple-lines is 8 mm. For the second one (i.e. dual balun 2), the input couple-line width is 2 mm and coupled-line space is 3 mm. The distance between output couple-lines is also 8 mm. The other geometric parameters of the two dual baluns are the same. In a star double-balanced mixer or a four-way power amplifier, the dual balun is applicable for four-way power splitting. Over the 92 ~ 96 GHz, dual balun 1 attains prominent S11 of −14.4~ −16.4 dB, S21 of −7.61~ −7.67 dB, S31 of −8.78~ −8.93 dB, S41 of −7.43~ −7.6 dB, S51 of −9.68~ −9.89 dB, amplitude imbalance magnitude (AIM) smaller than 2.39 dB, and phase difference deviation (PDD) smaller than 3.6°. Furthermore, dual balun 2 attains remarkable S11 of −13.8~ −14.8 dB, S21 of −7.8~ −7.95 dB, S31 of −8~ −8.39 dB, S41 of −7.46~ −7.72 dB, S51 of −8.18~ −8.54 dB, AIM smaller than 0.95 dB, and PDD smaller than 3.8°, close to those of dual balun 1.

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Abstract The design, materials, process, and fabrication of a heterogeneous integration of 4 chips by a FOPLP (fanout panel-level packaging) method are investigated in this study. Emphasis is placed on (a) the application of a dry-film EMC (epoxy molding compound) for molding the chips, and (b) the application of a special assembly process called Uni-SIP (uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508mm × 508mm. The package dimensions of the FOPLP are 10mm × 10mm. The large chip size and the small chip sizes are, respectively 5mm × 5mm and 3mm × 3mm.

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Abstract The design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this study. Emphasis is placed on (1) the application of a dry-film epoxy molding compound for molding the chips and (2) the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. Electroless Cu is used to make the seed layer, laser direct imaging is used for opening the photoresist, and printed circuit board (PCB) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508 × 508 mm. The package dimensions of the FOPLP are 10 × 10 mm. The large chip size and the small chip sizes are, respectively, 5 × 5 mm and 3 × 3 mm. The uniqueness of this study is that all the processes are carried out by using the PCB equipment.

A Miniature Endoscopic Optical Coherence Tomography Probe Based on C-Lens

We present a novel miniature endoscopic optical coherence tomography (OCT) probe based on an electrothermal microelectromechanical (MEMS) mirror and a C-lens. The MEMS mirror has a relatively large mirror plate of 0.5 mm × 0.5 mm on a small chip size of 1.5 mm × 1.3 mm, leading to the outer diameter of the endoscopic probe down to only 2.5 mm so that the probe is capable of being inserted through the biopsy channel of a conventional endoscope. A long focal length of 12 mm is achieved by properly designing the C-lens. Compared to commonly used GRIN lenses, C-lenses have advantages of much smaller sensitivities of the working distance and spot size to machining variations. The C-lens based probe can scan a large field of view (FOV) of 6 mm × 6 mm at only 5-V drive voltage. A swept source endoscopic OCT system is constructed using this miniature probe. Experiments show that the corresponding lateral and axial resolutions are about 50 and 14 μm, respectively. Various samples including human fingers, onions, and cancerous colon tissue are imaged and the result suggests this large-working-distance, large-FOV endoscopic probe is promising for applications in large tubular organs and large-area lesions.

Influence of chisel edge thinning on helical point micro-drilling performance

Chisel edge thinning can effectively improve the drilling performance of austenitic stainless steel. Four kinds of helical point micro-drills, each with a thinned chisel edge of a distinct length, are fabricated based on the mathematics models of the micro-drill by using a six-axis computer numerical control tool grinder. Micro-drilling experiments on 304 stainless steel are conducted. Drilling performance is evaluated according to the measured and observed micro-hole machining quality, chip morphology, thrust force, and tool wear of the micro-drill tip. With a decrease in the chisel edge length, the micro-holes drilled using thinned micro-drills have small entrance burrs, roundness errors, and regular shapes, which are attributed to an increase in self-centering capability. Owing to increased equivalent chip thickness and different directions of chip flow, micro-drills with thinned chisel edge can generate more small-size chips and improve chip breaking. In addition, the inner cutting edge with a positive rake angle replaces the chisel edge with a negative rake angle to cut the workpiece, significantly reducing the chip curl, thrust force, and tool wear of micro-drills. However, helical point micro-drills with critical chisel edge lengths by thinning exhibit less thrust force and tool wear than do helical point micro-drills with no chisel edge because of the increase in the uncut chip width of the micro-drill. Thus, with the selected parameter range, the optimal helical point micro-drill is the micro-drill with a specific chisel edge length by thinning to improve drilling performance.

APLIKASI MESIN SPINNER BERKECEPATAN RENDAH UNTUK MENURUNKAN KADAR AIR DAN MINYAK KERIPIK IKAN UKURAN BESAR DI UKM BERKAH

Rawa pening is a water area located in the Banyubiru area of Semarang Regency. Aside from being used<br />as a place for fish farming, the area around Rawa Pening is used as a tourist spot for example “Bukit Cinta”.<br />Around the location it will be easy to find entrepreneurs who provide souvenirs typical of these tourist locations.<br />The typical Bukit Cinta souvenirs is a variety of chips, including fish chips. There are 2 fish chips in Bukit Cinta,<br />small size chips and large size chips. The problem was the shelf life of large size chips is short because they<br />cannot be spinered so that the oil content is still high and than pronoun to oxidation. Low speed spiner tools can<br />be a solution to overcome existing problems. The results of the spinner machine application are obtained lower<br />moisture content and lipid content than products without being spinnered. Moisture content after the spinning<br />process using spiner machine, the wader chips was 3.25% and tilapia chips were 3.97%. While the wader chips<br />lipid content was 31.16% (bk) and tilapia chips 3.97% (db).

Fabrication and characterization of multi-stopband Fabry–Pérot filter array for nanospectrometers in the VIS range using SCIL nanoimprint technology

Miniaturization of optical spectrometers can be achieved by Fabry–Perot (FP) filter arrays. Each FP filter consists of two parallel highly reflecting mirrors and a resonance cavity in between. Originating from different individual cavity heights, each filter transmits a narrow spectral band (transmission line) with different wavelengths. Considering the fabrication efficiency, plasma enhanced chemical vapor deposition (PECVD) technology is applied to implement the high-optical-quality distributed Bragg reflectors (DBRs), while substrate conformal imprint lithography (one type of nanoimprint technology) is utilized to achieve the multiple cavities in just a single step. The FP filter array fabricated by nanoimprint combined with corresponding detector array builds a so-called “nanospectrometer”. However, the silicon nitride and silicon dioxide stacks deposited by PECVD result in a limited stopband width of DBR (i.e., < 100 nm), which then limits the sensing range of filter arrays. However, an extension of the spectral range of filter arrays is desired and the topic of this investigation. In this work, multiple DBRs with different central wavelengths (λc) are structured, deposited, and combined on a single substrate to enlarge the entire stopband. Cavity arrays are successfully aligned and imprinted over such terrace like surface in a single step. With this method, small chip size of filter arrays can be preserved, and the fabrication procedure of multiple resonance cavities is kept efficient as well. The detecting range of filter arrays is increased from roughly 50 nm with single DBR to ~ 163 nm with three different DBRs.

Uneven-Topography-Chip Packing Approach Using Double-Self-Assembly Technology for 3-D Heterogeneous Integration

Although chip-level heterogeneous integration has high yield for production, low-throughput issue of chip-to-wafer bonding is necessary to be improved. Due to the uneven topography and small chip size, handling issue and alignment accuracy are important factors that impact the difficulty in heterogeneous integration. Self-assembly technology has a high potential to be applied in 3-D heterogeneous integration. By using hydrophobic film to define the stacking area, hydrophilic chips can be assembled to realize alignment process on these areas through wafer surface tension in a very short time. With this concept, double-self-assembly technology is accomplished to resolve both handling and alignment issues for uneven-topography-chip integration. In this paper, different chip sizes of $\mu $ -pillar are simulated to investigate the optimal water volume for double-self-assembly process. High alignment accuracy of misalignment measurement can be accomplished with the optimal water volume. Furthermore, microstructure of Cu/In bonded structures and corresponding electrical analyses are evaluated, while various reliability tests are investigated for bonding quality. Excellent results verify that the double-self-assembly technology could be applied to 3-D heterogeneous integration for uneven-topography-chip integration.

A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

Asymmetric seesaw structure of microelectromechanical systems accelerometer for sensing out-off-plane acceleration

A microelectromechanical systems (MEMS) accelerometer estimates the acceleration by detecting a difference in capacitance. This paper presents a small MEMS accelerometer with an asymmetric seesaw design. It was fabricated using a bulk machining process and accurately measures the applied acceleration based on a difference in capacitan ce. The large torque proof mass and chamfered structure of the torsional spring on the small chip were optimized to improve the device sensitivity and robustness of the design structure, respectively, which were the main factors in improving the MEMS sensor performance and maintaining the small chip size. After fabrication, we verified the design optimization by measuring the capacitance–voltage (C–V) curve behavior of the seesaw and making observations using scanning electron microscopy (SEM). The measured capacitance and theoretical calculation results were 249fF and 239.9fF, respectively. The SEM observations showed that there was no severe undercutting in the cross section of the structure. According to a finite element method analysis in just the electrical domain, the electrostatic characteristics such as the C–V measurements matched the theoretical values (within 3.6%). Moreover, the sensitivity of the fabricated accelerometer was 11.3fF/g, and the nonlinearity was 0.62% over the typical range of 1g. According to the system test results, the accelerometer had cross-sensitivity values of 0.06% (x/z axis) and 2.58% (y/z axis).

A Brief Review of OPT101 Sensor Application in Near-Infrared Spectroscopy Instrumentation for Intensive Care Unit Clinics.

The optoelectronic sensor OPT101 have merits in advanced optoelectronic response characteristics at wavelength range for medical near-infrared spectroscopy and small-size chip design with build-in trans-impedance amplifier. Our lab is devoted to developing a series of portable near-infrared spectroscopy (NIRS) devices embedded with OPT101 for applications in intensive care unit clinics, based on NIRS principle. Here we review the characteristics and advantages of OPT101 relative to clinical NIRS instrumentation, and the most recent achievements, including early-diagnosis and therapeutic effect evaluation of thrombus, noninvasive monitoring of patients' shock severity, and fatigue evaluation. The future prospect on OPT101 improvements in noninvasive clinical applications is also discussed.

Behavioral inferences from the high levels of dental chipping in Homo naledi.

A variety of mechanical processes can result in antemortem dental chipping. In this study, chipping data in the teeth of Homo naledi are compared with those of other pertinent dental samples to give insight into their etiology. Permanent teeth with complete crowns evidencing occlusal wear were examined macroscopically. The location, number, and severity of fractures were recorded and compared to those found in samples of two other South African fossil hominin species and in samples of nonhuman primates (n=3) and recent humans (n=7). With 44% of teeth affected, H. naledi exhibits far higher rates of chipping than the other fossil hominin samples. Specifically, 50% of posterior teeth and 31% of anterior teeth display at least one chip. The maxillary teeth are more affected than the mandibular teeth (45% vs 43%, respectively), 73% of molar chipping occurs on interproximal surfaces, and right teeth are more often affected than left teeth (50% vs 38%). Results indicate that the teeth of H. naledi were exposed to acute trauma on a regular basis. Because interproximal areas are more affected than buccal and posterior teeth more than anterior, it is unlikely that nonmasticatory cultural behavior was the cause. A diet containing hard and resistant food, or contaminants such as grit, is more likely. The small chip size, and steep occlusal wear and cupped dentine on some molars are supportive of the latter possibility. This pattern of chipping suggests that H. naledi differed considerably-in terms of diet, environment, and/or specialized masticatory processing-relative to other African fossil hominins.

A 0.7 V 6.66–9.36 GHz wide tuning range CMOS LC VCO with small chip size

ABSTRACTThe circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is −110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about −1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about −180.7 and −191.25 dBc/Hz, respectively. The chip area is 0.429 mm2 excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.

An Ultra-Low Power CMOS LNA for WPAN Applications

In this letter, an integrated CMOS LNA has been designed for low-rate wireless personal area network applications in $0.18~\mu $ m technology, by employing various low-power techniques. In order to achieve ultra-low power consumption and small chip size, an inductorless LNA with triple cross-coupling technique working in the subthreshold region has been designed. These techniques provide a high gain, low noise figure (NF) and ultra-low power consumption. The trade-off of the circuit has been discussed. Measured results have been shown: an average 17 dB gain, 4.2 dB NF while dissipating only 0.2 mW (LNA core) power from 1 V DC supply voltage and occupies only 0.27 mm2 area. These are considered to be state-of-the-art for 400 MHz~1 GHz CMOS WPAN applications.

Modification of oscillation modes in low frequency vibration assisted drilling

Low frequency vibration assisted drilling (LFVAD) is applied to generate small chip sizes in order to avoid chip accumulation in drilling processes. In contrast to ultrasonic assisted drilling the oscillations are characterized by relatively high amplitudes of up to 200 µm at significantly lower maximum frequencies of around 300 Hz. This enables an interrupted cut which leads to a chip breakage, almost independent of the mechanical properties of the workpiece material. However, significantly higher cutting forces are generated in comparison to conventional drilling processes (at the same material removal rate). In the present study the shape of the vibration oscillations (which is usually sinusoidal) was modified in order to affect the uncut chip shapes. The geometrical cutting conditions have been visualized using a kinematic cutting model. Due to the modification of the oscillation mode the maximum cutting forces could be decreased by at least 13 %. Furthermore, the cutting force progression during the generation of each pair of chips (two fluted cutter) could be improved regarding a smoother slope of the forces. As a consequence, “shock loads” to the tools are avoided and higher values of the axial feed are enabled, which contributes to a raise of productivity in LFVAD.

Design of efficient power amplifier for low power transmitters

This paper presents a fully integrated, low transmit-power and high-efficiency 2.4 GHz class-E power amplifier (PA) in TSMC 0.18 μm CMOS process for low-power transmitters such as wireless sensor networks (WSN). In this paper, a new output load has been proposed. Also, analytical design equations have been included to design an efficient low power circuit. This PA, employs the pad capacitance and bond-wire inductance of the output node, for satisfying class-E zero-voltage switching (ZVS) condition and matching the antenna's 50 Ω resistance. By using bond-wire inductance instead of inductor in the output filter, smaller chip size and higher efficiency has been achieved compared to other works for low transmit-power applications. Also, the effectiveness of bulk-drive technique on faster switching and increasing efficiency have been evaluated. It has been proved that this technique leads to increase the efficiency of switching PAs. This PA delivers a range of output power from 2.7 to 7.2 dBm with a supply voltage range from 500 to 850 mV while achieving overall power efficiency range of 57.3---60.7%.