An Ultra-Low Power CMOS LNA for WPAN Applications

Abstract

In this letter, an integrated CMOS LNA has been designed for low-rate wireless personal area network applications in $0.18~\mu $ m technology, by employing various low-power techniques. In order to achieve ultra-low power consumption and small chip size, an inductorless LNA with triple cross-coupling technique working in the subthreshold region has been designed. These techniques provide a high gain, low noise figure (NF) and ultra-low power consumption. The trade-off of the circuit has been discussed. Measured results have been shown: an average 17 dB gain, 4.2 dB NF while dissipating only 0.2 mW (LNA core) power from 1 V DC supply voltage and occupies only 0.27 mm2 area. These are considered to be state-of-the-art for 400 MHz~1 GHz CMOS WPAN applications.