Sleepy Keeper Research Articles

Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale Technologies

In latest wired and wireless communication equipment, VCO (voltage-controlled oscillator) is the major building block and particularly used as the stable high frequency clock generator. VCO performance is measured through frequency range, power supply used, area occupied, power consumption, delay, and phase noise. VCO is the cascaded of odd number of inverter stages in a ring format, hence it is also articulated as a ring oscillator. Today’s portable communication devices are battery operated. Hence, low power and area efficient designs play a key role in battery life enhancement and device size reduction. Device scaling improves the effective silicon area utilization, but it leads to more leakages. Therefore, low power techniques along with the technology scaling is the best way of low power designs. In this article, discussed various low power schemes. The ring oscillator designs are carried out in various nano meter scaled technologies such as 180nm, 90nm,65nm and 45nm. A 5-stage ring oscillator is implemented in each technology along with low power schemes, simulated in Cadence virtuoso, and noted power, delay, and area. Observed that the proposed ring oscillator with sleepy keeper technique generated a stable frequency of oscillations in the range of 1GHz-2GHz. A control voltage of 1.8V to 0.4V is applied and targeted the power less than 30mW and delay in 0.25p sec.

Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques

This paper presents the sleepy keeper and drain gating technique to improve the performance of 10T SRAM cell. The behavior of 10T SRAM cell is evaluated using benchmarked industry standard GPDK 45nm Technology Node of the Cadence Virtuoso EDA tool. The performance is analyzed in terms of dynamic and static parameters of 10T SRAM cell and compared with 6T SRAM, where find the reduction in dynamic power and static power dissipation. Besides this, observed the reduction in leakage current using sleepy keeper and drain gating technique. The proposed modified topology applicable in single-ended write and differential read operation. The read delay product and the write delay product is decreased by 36.7 % and 67.5 %, respectively. The major goal of the suggested architecture is to provide the improved stability, reduction in delay, as well as reduction in leakage current.

Low Power Reduction Techniques Implementation and Analysis in Sense Amplifier Circuit Configurations

MTCMOS (Multi-Threshold CMOS), sleepy stack, sleepy keeper, and footer stack are examples of low power saving techniques incorporated into the core gpdk 90nm technology papers used in the proposed study using Cadence. The main focus of these tests is the power consumption of various sense amplifier circuits. The simulation results show that the charge-transfer sense amplifier uses much less energy than voltage and current sense amplifiers. The present mode detecting amplifier’s power consumption can be decreased by up to 98 percent by using MTCMOS technology.

Leakage power optimization using sleeping approaches in TSPC D flip-flop

In this paper, the basic D flip-flop has been considered with TSPC (True Single-Phase Clock) logic. Here, the leakage power of 1031 pW fell to the power for the operation of the memory elements, which is a lot compared to other triggers. The challenge is to reduce the optimal power off to conserve idle power. To solve this problem, three different powersaving techniques were considered, such as Technique 1: sleeping transistors, Technique 2: sleepy stack, and Technique 3: sleepy keeper. In a comparative study, it was observed that Technique 1 is the most optimal method for delays (falling and rising) and off-state leakage power compared to the other methods considered. The off-state leakage power was 1.753 pW, which is 93.07% and 76.90% less than by Techniques 2 and 3, respectively.

ROBUST AND SECURE S-BOX DESIGN WITH GATED HYBRID ENERGY RECOVERY LOGIC (GHERL) FOR IOT APPLICATIONS

The smart Internet of Things (IoT) network relies heavily on data transmission over wireless channels. Hence, it should be designed to be robust against the attacks from hackers and antagonists. The confidentiality in IoT devices is directly proportional to the complexity and power consumption. To mitigate these issues, this paper proposes a secure Substitution Box (S-Box) design that is exploited in the IoT for cyber security applications. The S-Box is based on Gated Hybrid Energy Recovery Logic (GHERL) that is an amalgamation of two different techniques as adiabatic logic and power gating. Adiabatic logic is preferred to attain high energy efficiency in practical applications such as portable and handheld devices. Power gating technique is preferred to reduce the leakage power and energy consumption. The proposed GHERL XOR gate and S-Box are implemented with 125nm technology in Tanner EDA tool. The consequences of the experiments exhibits that the novel S-Box design with GHERL XOR decreases the power consumption by 1.76%, 35.26%, 36.81%, 41.01% and reduces the leakage power by 58.54%, 20.27%, 27.38%, 13.63% when compared with the existing techniques such as S-Box with sleep transistor, dual sleep transistor, dual-stack and sleepy keeper approach. Keywords: Adiabatic logic, Power Gating, Internet of Things, S-Box

Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability

Remarkable progress in the field of wireless communication has created a research interest for Viterbi decoder with long duration of battery life, low power dissipation and portabilty in the application. Such a low power Viterbi decoder is required in the area of high speed data transfer application like communication in the convolutional coding for error free inforamtion. This article propose two strategies to enhance the execution of the decoder by circuit level design of the Viterbi decoder utilizing a sleepy keeper method with additional leakage current control transistors, which decreases the leakage power dissipation. Then at the survivor memory unit the variation is done by the usage of modified resister exchange method with search space pruning. The Simulation of the work at the semiconductor level is done with 90 nm TSMC T-SPICE and SPICE netlist is used to create the simscape application of decoder which is applied in the Matlab Communication toolbox. The outcome of the system determines that the proposed sleepy keeper Viterbi Decoder in WLAN application has a reduction of 0.24 % with QPSK and 0.13 % reduction with QAM. Also, the SNR is found to be improved at a rate of 0.5db when compared with code based Viterbi decoder.

VLSI Implementation Of High Speed Low Power Design Using Hybrid Power Gating Technique

Nowadays, low powerhigh speed CMOS design is one among the challenging issues. As the technology is scaling down, the static power consumption has turned into a remarkableconcern. The proposed methodology incorporates the following technique such as sleep technique, stack technique, sleepy stack technique, sleepy keeper technique, leakage control transistor technique (LECTOR) and sleepy keeper leakage control transistor technique (SK-LCT) for leakage power reduction. The proposed power gating techniquelead to low power,high speed CMOS design. The xor gate, xnor gate, half adder & 6T sram cell is outlined using newly proposed power gating technique for a low power high speed design.When compared to the conventional methodology xor gate saves 19.95 % of power & 33.75% of delay, xnor gate saves 12 % of power & 23.29 % of delay, half adder saves 35.29% of power &25.69% of delay and sram cell saves 14.29% of power & 34.37 % of delay. Simulation is done using Tanner EDA tool and the outcomes demonstrate a noteworthy change in leakage power utilization and speed.

Efficient design of dual controlled stacked SRAM cell

In low power VLSI circuit designs, power dissipation is one of the challenging issues which is associated with threshold voltage. The reduction of threshold voltage increases the subthreshold leakage current by increasing the leakage power dissipation which plays an important role in total power dissipation. Due to this leakage power issue, the devices which are operated by battery for a long time in standby mode drained out as soon. To mitigate this problem Static Random-Access Memory (SRAM) is designed with dual control stacked inverter which exploits dual control signals. The proposed dual control stacked inverter reduces the power consumption by 43.42%, 71.71% 63.83% and reduces the delay by 77.05%, 77.06%, 77.16% when compared to sleepy stack approach, sleepy keeper approach and dual stack power gating. Similarly, the proposed dual controlled stacking SRAM with low Vth reduces the power consumption by 96.7%, 95.36%, 96.69% and 33.54% when compared to the sleepy stacky approach, sleepy keeper approach, dual stack approach and dual controlled stacking. The proposed SRAM cell increases the reliability of overall System on Chip.

Implementation and analysis of Leakage Reduction Techniques in 6T SRAM cell

Leakage power dissipation is the dominating parameter while calculating in total power consumption of CMOS circuits specially in SRAM cells at 90 nm technology. In modern System on chips (SOCs), SRAM plays an important role because 70 to 80 percent area of any SOC is occupied by memory. So it is important to take care of leakage power dissipation and delay of memory based circuits. In this research paper, SRAM cell with hybrid Sleepy Keeper and Stack approach is proposed to optimize both the above parameters. SRAM cell using hybrid Sleepy Keeper and Stack approach leakage power consumption is 49.9 percent less and its dynamic power dissipation is 28% to 53% less as correlated to other implemented approaches. Read delay and power delay product of SRAM cell with hybrid Sleepy Keeper and Stack approach is less as compared to SRAM cell with Sleepy keeper and SRAM cell using Variable body biasing approach but these parameters value are more as correlated to conventional 6T SRAM cell and SRAM cell using stack approach.

Disigning A Novel Architecture to Reduce Stand by and Dynamic Power Dissipation for Sleepy Keeper Cmos Logic Circuits

Disigning A Novel Architecture to Reduce Stand by and Dynamic Power Dissipation for Sleepy Keeper Cmos Logic Circuits

WITHDRAWN: Comparative analysis on low power SRAMs

Abstract Static Random Access memory (SRAM) has become an important role due to their low access time and storage capacity. The Static Random Access Memory (SRAM) has a significant impact on the overall power consumption and energy efficiency. The leakage power in SRAM is one of the most significant problems when technology node is scaling down. The main concept of this survey is to compare various Low power SRAMs based on their power consumption as well as delay in the SRAM. Different types of power reduction techniques like power gating, sleepy keeper leakage control transistor technique (SK-LCT), Gated ground sleep logic, LECTOR and MTCMOS techniques, etc.. are applied to the SRAM to reduce the power consumption and various parameters like leakage power, delay, speed and Static Noise Margin (SNM) in different EDA tools like Tanner, Cadence, Silvaco TCAD etc., This comparative analysis conclude that forced sleep technique is reduces power consumption and up to 40% and 43% respectively when compared with other technique. This comparative analysis helps the designer and researchers to get the overview of all the available techniques with their results, so they can choose the best techniques based on their specific requirements.

Low power sleepy keeper technique based VLSI architecture of Viterbi decoder in WLANs

ABSTRACT .Wireless communication technologies have advanced from cellular networks to satellite systems which create an advancing demand for low power battery operated decoding unit. Widely used error correction technique in the wireless communication systems is the channel coding. In channel coding, convolutional codes are commonly used for the transmission of data over a noisy channel. The methodologies adopted in the proposed design to achieve low power and increase in performance is by designing the architecture of the Viterbi decoder at circuit level design using a sleepy keeper technique, which curtails the leakage power dissipation. The second method is by including the modified register exchange algorithm, which reduces the occurrence of error probability with low power in signal transmission in the wireless domain. Simulation of the design is executed in 45nm TSMC in Tanner-SPICE. Promising results are obtained with reduction in power 31.54% with the CMOS technology for the WLAN frequency of 2.5MHz. BER performance of the design also found to be low in the channel environment.

Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design

This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique for nano scale VLSI technologies. Eight prior techniques are taken for comparison with proposed technique on 65[Formula: see text]nm technology. All the techniques are applied on four benchmark circuits: XOR gate, 1-bit adder, 1-bit comparator and 4-bit up-down counter for measurement of area consumption and total power dissipation. The proposed SC-SS technique achieved very high power efficiency as compared to Complementary CMOS technique (CCT), Dual sleep Technique (DST), Forced stack technique (FST), Sleepy keeper technique (SKT), Sleepy pass gate technique (SPGT), Sleep transistor technique (STT) and VLSI CMOS Circuit Leakage Reduction technique (VCLEARIT). Although Sleepy stack technique (SST) is power efficient as compared to SC-SS technique, this is on the expense of area and delay penalty. Proposed technique has shown the area improvement of 33% for XOR, 10.78 % for 1-bit adder, 14.9% for 1-bit comparator and 9.7% for 4-bit up-down counter over SST technique on 65[Formula: see text]nm technology. At the same time, power-area product of SC-SS is 29.56% and 54.96% less as compared to SST for XOR and 4-bit up-down counter. To obtain the efficiency of proposed technique over SST in terms of delay and power-delay product, basic inverter design is taken into consideration. Delay of SC-SS inverter is 34.8% and power-delay product is 6.9% less as compared to SST inverter on 65[Formula: see text]nm technology.

Proficient Static RAM design using Sleepy Keeper Leakage Control Transistor & PT-Decoder for handheld application

Due to their large storage capacity and small access time static random access memory (SRAM) has become a vital part in numerous VLSI chips. Low power adequate memory configuration is a standout among the most challenging issues in SRAM design. As the technology node scaling down, leakage power utilization has turned into a noteworthy issue. In this paper a novel power gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application. The SRAM architecture has two primary components, specifically SRAM cell and sense amplifier. The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. The outline of SRAM architecture utilizing pass transistor decoder (PT-Decoder) gives better outcomes in term of power. Simulation is done using Tanner EDA tool in 180nm technology and the results demonstrate a noteworthy change in leakage power utilization and speed.

Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation.

Study and Analysis of CMOS Carry Look Ahead Adder with Leakage Power Reduction Approaches

Background/Objectives: This paper represents the implementation of carry look ahead adder using different leakage power reduction techniques like sleepy approach, stack approach, sleepy stack approach and sleepy keeper approach. Effecting the static power dissipation high, the threshold voltage (Vth) is reduced that has granted tremendously towards the growth in the sub threshold leakage power. Here conventional 4-bit carry look ahead adder is designed by adopting 1-bit full adders and carry look ahead blocks. Methods/Statistical Analysis: In this paper, an extensive study and analysis of different leakage power minimization approaches have been implemented. In the comparative analysis carry look ahead adder is designed using different leakage power reduction approaches like sleepy, stack, sleepy stack and sleepy keeper. The circuits are implemented on Tanner EDA tool at 250 nm Technology and considered PMOS, NMOS as typical models. From this paper work that only an applicable selection of leakage power reduction approach for a particular function will be well borne by a Very Large Scale Integrated (VLSI) circuit design depend on progressive analytical method. Findings: The average power, delay and number of transistors are calculated in the tanner tool for carry look ahead adder using all the four approaches. Applications/Improvements: The analytical study is implemented in the real time applications while constructing adders.

Comparison of Leakage Power Reduction Techniques in 65nm Technologies

The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. Leakage power consumption is one of the major technical problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper comparison of Leakage reduction technique is developed in Cadence Virtuoso in 65nm regime with the combination of stack with sleepy keeper approach with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%, Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24% with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.

Design of Low Leakage Multi Threshold (Vth) CMOS Level Shifter

In this paper, a low leakage multi V th level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using MTCMOS technique and sleepy keeper. MTCMOS is an effective circuit level technique that improves the performance and design by utilizing both low and high threshold voltage transistors. Leakage power dissipation has become an overriding concern for VLSI circuit designers. In this a “sleepy keeper” approach is preferred which reduces the leakage current while saving exact logic state. The new low-power level shifter using sleepy keeper is compared with the previous work for different values of the lower supply voltage. When the circuits are individually analyzed for power consumption at 45nm CMOS technology, the new level shifter offer significant power savings up to 37% as compared to the previous work. Alternatively, when the circuits are individually analyzed for minimum propagation delay, speed is enhanced by up to 48% with our approach to the circuit. All the simulation results are based on 45nm CMOS technology and simulated in cadence tool. DOI: http://dx.doi.org/10.11591/ijece.v3i5.3166

Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits

of transistor features sizes has improves performance, increase transistor density and reduces the power consumption. A chip's maximum power consumption depends on its technology as well as its implementation. As technology scales down and CMOS circuits are powered by lower supply voltages, standby leakage current becomes significant. As the threshold voltage is reduced due to scaling, it leads to increase in sub threshold leakage current and hence increase in static power dissipation. This paper presents performance analysis of inverter using conventional CMOS, stack and dual threshold transistor stacking, sleepy stack, sleepy keeper technique etc. The performance analyses of inverter were analyzed in 90nm technology using Virtuoso software (cadence). In order to reduce the static power dissipation, one has to sacrifice circuit performance and area. This paper presents the comparative study of all the approaches. The sleepy stack and variable body biasing approach shows improved results in terms of static power.

Design and Analysis of Low Power CNTFET TSPC D - Flip Flop Based Shift Registers

This paper enumerates the efficient design and analysis of low power CNTFET True single phase clock logic D Flip flop based shift registers. The TSPC D flip flop and shift registers are designed using Stanford University CNTFET model and proposed 10nm CNTFET model with sleepy keeper low power technique. The CNTFET is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage of 1V and the operating frequency at 1GHz. The simulation results are obtained and the analysis are compared with circuits designed using 32nm MOSFET. The comparison results are indicated that the proposed 10nm CNTFET based design and the low power technique are more efficient in power saving as compared to MOSFET design.