Efficient design of dual controlled stacked SRAM cell

Abstract

In low power VLSI circuit designs, power dissipation is one of the challenging issues which is associated with threshold voltage. The reduction of threshold voltage increases the subthreshold leakage current by increasing the leakage power dissipation which plays an important role in total power dissipation. Due to this leakage power issue, the devices which are operated by battery for a long time in standby mode drained out as soon. To mitigate this problem Static Random-Access Memory (SRAM) is designed with dual control stacked inverter which exploits dual control signals. The proposed dual control stacked inverter reduces the power consumption by 43.42%, 71.71% 63.83% and reduces the delay by 77.05%, 77.06%, 77.16% when compared to sleepy stack approach, sleepy keeper approach and dual stack power gating. Similarly, the proposed dual controlled stacking SRAM with low Vth reduces the power consumption by 96.7%, 95.36%, 96.69% and 33.54% when compared to the sleepy stacky approach, sleepy keeper approach, dual stack approach and dual controlled stacking. The proposed SRAM cell increases the reliability of overall System on Chip.