Implementation and analysis of Leakage Reduction Techniques in 6T SRAM cell

Abstract

Leakage power dissipation is the dominating parameter while calculating in total power consumption of CMOS circuits specially in SRAM cells at 90 nm technology. In modern System on chips (SOCs), SRAM plays an important role because 70 to 80 percent area of any SOC is occupied by memory. So it is important to take care of leakage power dissipation and delay of memory based circuits. In this research paper, SRAM cell with hybrid Sleepy Keeper and Stack approach is proposed to optimize both the above parameters. SRAM cell using hybrid Sleepy Keeper and Stack approach leakage power consumption is 49.9 percent less and its dynamic power dissipation is 28% to 53% less as correlated to other implemented approaches. Read delay and power delay product of SRAM cell with hybrid Sleepy Keeper and Stack approach is less as compared to SRAM cell with Sleepy keeper and SRAM cell using Variable body biasing approach but these parameters value are more as correlated to conventional 6T SRAM cell and SRAM cell using stack approach.