Design of Low Leakage Multi Threshold (Vth) CMOS Level Shifter

Abstract

In this paper, a low leakage multi V th level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using MTCMOS technique and sleepy keeper. MTCMOS is an effective circuit level technique that improves the performance and design by utilizing both low and high threshold voltage transistors. Leakage power dissipation has become an overriding concern for VLSI circuit designers. In this a “sleepy keeper” approach is preferred which reduces the leakage current while saving exact logic state. The new low-power level shifter using sleepy keeper is compared with the previous work for different values of the lower supply voltage. When the circuits are individually analyzed for power consumption at 45nm CMOS technology, the new level shifter offer significant power savings up to 37% as compared to the previous work. Alternatively, when the circuits are individually analyzed for minimum propagation delay, speed is enhanced by up to 48% with our approach to the circuit. All the simulation results are based on 45nm CMOS technology and simulated in cadence tool. DOI: http://dx.doi.org/10.11591/ijece.v3i5.3166