Sleep Transistor Research Articles

Low Leakage CNTFET SRAM Cells

This paper presents different low-leakage power Carbon NanoTube FET (CNTFET) based SRAM cells at nano technology. These SRAM cells are obtained by applying different circuit level leakage power reduction techniques called Sleep transistor, Forced stack, Data-Retention sleep transistor and Stacked sleep. All these cells are designed and simulated to assess their performance. All these techniques are compared in terms of leakage power, dynamic power, read delay, write delay, SNM and Area. Among all the SRAM cells, stacked sleep CNTFET SRAM cell is best in terms of leakage power saving with state saving capability.

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.

Power-Gating Single-Rail MOS Current-Mode Logic Circuits Using High- Threshold PMOS Transistors as Linear Resistors

In this paper, a power-gating technology for single-rail MOS Current Mode Logic (SRMCML) circuits is pre- sented, which use the high-threshold PMOS transistors as linear load resistors to reduce the power dissipation in the sleep mode. The basic SRMCML cells, such as buffer/inverter, AND2/NAND2, AND3/NAND3, OR2/NOR2, OR3/NOR3, XOR2/XNOR2, multiplexer, and 1-bit full adder, are used to verify the effectiveness of the proposed power-gating scheme. The equivalent model for calculating energy dissipations of the power-gating SRMCML circuits is constructed. All circuits are simulated with HSPICE at a 130 nm CMOS process. By simulating power-gating SRMCML circuits in active and sleep modes, it is concluded that the power dissipation of power-gating SRMCML circuits in sleep mode is reduced with the decrease of the device sizes of high-threshold PMOS sleep transistors, while the power dissipation of power-gating SRMCML circuits is almost independent of the device sizes of sleep transistors in active mode. The power dissipation comparisons among power-gating SRMCML, conventional SRMCML, and power-gating static CMOS circuits are carried out. The power dissipation of the proposed power-gating SRMCML circuits is the least among the three above mentioned structures.

FELERION: a new approach for leakage power reduction

The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%–94% as compared to the conventional approach.

A design of low swing and multi threshold voltage based low power 12T SRAM cell

This paper focuses on the design of a novel low power twelve transistor static random access memory (12T SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines, respectively. Reduction in swing voltage reduces the dynamic power dissipation when the SRAM cell is in working mode. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep to active (OFF to ON condition) and active to sleep (ON to OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell. Simulation has been done in 45nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose.

BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs

Power gating is an effective way to reduce leakage power. This technique uses high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> transistors, called sleep transistors, to turn off the power supply. However, sleep transistors suffer from the bias temperature instability (BTI) effect, resulting in an increased V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> , and reduced reliability. This paper proposes two BTI-aware sleep transistor sizing algorithms to reduce the total width of sleep transistors based on the distributed sleep transistor network structure. The proposed algorithms reduce total width by more than 16.08%. More area can be reduced if the BTI effect on both sleep and cluster transistors is considered.

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT

In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

Low Power dissipation of Ring Counter using Dual sleep Transistor approach

Low Power dissipation of Ring Counter using Dual sleep Transistor approach

Analyzing the Impact of Bootstrapped ADC with Augmented NMOS Sleep Transistors Configuration on Performance Parameters

This paper represents an efficient bootstrapped analog to digital converter with augmented NMOS sleep transistors. The newly designed MOS-based bootstrapped circuit is implemented to provide controlled input supply for analog to digital converter to develop the enhancing capability of circuit. This will reduce the effective leakage of the circuit. In the second stage, the NMOS sleep transistors are augmented as pull-up and pull-down transistors. Due to augmentation of transistors, controlled power supply ( $$V_{\mathrm{DD}})$$ V DD ) is obtained. Because of this, current driving capability in MOS transistors is improved and minimum sub-threshold leakage current is formed. Due to this, reduction of leakage power dissipation occurs much effectively. The whole simulation has been done at 45 nm (nanometer) technology. It is realized that the leakage power is reduced till 50 % approximately and delay performance is improved. It means that speed is improved using bootstrapped circuit with augmented sleep transistors NMOS. In this paper, different consecutive designs with Analog to Digital converter are represented.

Reduction of Leakage Power using Stacking Power Gating Technique in Different CMOS Design Style at 45Nanometer Regime

As transistor sizes scale down and levels of integration increase, leakage power has become a vital downside in modern low-power VLSI technology. This is often very true for ultra-lowvoltage (ULV) circuits, wherever high levels of leakage force designers to selected relatively high threshold voltages, which limits performance. In this paper, we design different design approach of master slave D flip-flop with stacking power gating leakage reduction technique. Here these techniques essentially increase the effective resistance of leakage paths by adding sleep transistors between logic stacks and power supply rails. Power gating technique also provides many of the property from transistor stacking technique. The proposed approach saves maximum amount of the Leakage power without degrading the performance of the circuit. In this work we analyses the leakage power of three different types of CMOS design style such as pass transistor logic (PTL), transmission gates and gate diffusion input (GDI) design. All these proposed circuits are simulated with and without the application of leakage reduction techniques. The circuits are simulated using Cadence Virtuoso tool at 45nm technology for various parameters.

Design and optimization of Flash type Analog to Digital converter using Augmented Sleep Transistors with Current Mode Logic

This paper represents the low leakage & the delay performance optimization of Flash type Analog to Digital converter using Augmented Sleep Transistors with Current Mode Logic (ASTCML) at 45 nm technology. It is realized that the leakage power is reduced 50% approximately in ASTCML logic based analog to digital converter design at 1 V supply voltage. Due to reduced leakage power, the probability of causing thermal runaway is decreased and the design stagnation is increased. Even though the featured analog to digital converter is designed using combination of PMOS & NMOS. The anticipated analog to digital converter is appropriate for high speed and wireless network application. In this paper, different consecutive designs with flash type analog to digital converter are represented.

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar transistors, are devices whose polarity is online reconfigurable by changing the second gate bias. In this brief, we exploit the online control of ambipolar device polarity to achieve intrinsically power-gated DCVSL circuits bypassing the use of series sleep transistors. We perform circuit-level simulations and comparisons at 22-nm technology node, considering silicon nanowire -based DG controllable-polarity FETs. Experimental results show that ambipolar DCVSL circuits power gated by the proposed technique have on average 6× smaller standby power with only 1.1× timing penalty with respect to their non-power-gated versions. As compared with unipolar FinFET-based realizations, our proposal is capable to reduce up to 1.9× the standby power consumption of a low-standby-power process and, at the same time, increase up to 10% the performance of a high-performance process.

HIGH PERFORMANCE NOVEL DUAL STACK GATING TECHNIQUE FOR REDUCTION OF GROUND BOUNCE

The development of digital integrated circuits is c hallenged by higher power consumption. The combinat ion of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth i n power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to redu ce the leakages in the circuit many low power strategies are identified an d experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EM F of the ground connection we are calling it as ground bounce noise. To reduce this n oise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and i mplementation includes header or footer switch sel ection, sleep transistor distribution choices and sleep transistor gate len gth, width and body bias optimization for area, lea kage and efficiency. Novel dual stack technique is proposed that reduces not only t he leakage power but also dynamic power. The previo us techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed a nd the conditions for the important design parameters (Minimum ground bounce noise) hav e been derived. The Monte-Carlo simulation is perf ormed in Microwind to calculate the values of all the needed parameters f or comparison.

Design of Static Random Access Memory for Minimum Leakage using MTCMOS Technique

This work involves implementation of 8x8 SRAM using Multi Threshold CMOS (MTCMOS) technique which reduces the leakage power by placing sleep transistor either between ground and pull-down network or VDD and pull up network. SRAM is designed using D-Latch. As reduction in the leakage power is more by using PMOS sleep transistor compared to NMOS sleep transistor, this design is implemented using MTCMOS technique with PMOS as sleep transistor. The design can be used where low power is the constraint, as it offers 86% of power savings.

Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications

The Analog to Digital converters (ADC) play a very important role in today’s world of electronic systems. The requirement of present applications demands high speed, low power dissipation, minimum area, low noise and application specific resolution. Out of the various types of ADCs available the flash ADC is most popular for its highest conversion rate and its wide applications. On the down side the flash ADC dissipates high power due to the presence of resistance ladder. The power dissipation further increases with increase in resolution. In this research two different approaches are presented which eliminates the resistor ladder completely and hence reduce the power demand drastically. The first approach is Switched Inverter Scheme (SIS) ADC; it is realized for 3 bits using 7 comparator circuits of varying size in CMOS 45nm technology with Predictive Technology Model (PTM). The test result obtained indicates an offset error of 0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of 0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 µwatts; Power delay product (PDP) is 415.9 fWs, and the area overhead is 1.89µm 2 . The second approach is Sleep transistor SIS ADC. This approach shows 71% improvement in power dissipation. Whereas PDP is found to be 107.3 fWs and area overhead is 1.94 µm2 for Sleep transistor SIS ADC.

A HIGH-LEVEL TECHNIQUE FOR ESTIMATION AND OPTIMIZATION OF LEAKAGE POWER FOR FULL ADDER

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.

LEAKAGE POWER REDUCTION IN CMOS CIRCUITS USING LEAKAGE CONTROL TRANSISTOR TECHNIQUE IN NANOSCALE TECHNOLOGY

In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage problem in CMOS circuits, uses two additional leakage control transistors, which are self-controlled, in a path from supply to ground which provides the additional resistance thereby reducing the leakage current in the path. The main advantage as compared to other techniques which involves the sleep transistor is that LECTOR technique does not require any additional control and monitoring circuitry, thereby limits the area increase and also the power dissipation in active state. Along with this, the other advantage with LECTOR technique is that it does not affect the dynamic power which is the major limitation with the other leakage reduction techniques.

Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications

This paper investigates both electrostatic control improvement and performance enhancement of UTBB SOI MOSFETs obtained in quasi-double-gate (QDG) regime (i.e. simultaneously biasing top- and back-gate (substrate or ground plane) as Vbg=k·Vg) as a strong function of k-multiplication factor, when compared to a standard single-gate mode. Improved performance (in terms of transconductance, drive current and early voltage) in QDG mode combined with lowered DIBL and enhanced gain are of interest for high-precision low-frequency analog applications. QDG mode is demonstrated to allow threshold voltage tuning, subthreshold swing reduction and on-current enhancement without off-state current degradation, thus of interest for digital applications. The unique feature of QDG mode is finally exploited to boost the performances of the sleep transistor in the practical use case of a power-gated processor. About 30% reduction of the leakage in stand-by mode is achieved at nominal Vg with a Vbg of 3V, which can be generated at marginal area/power overheads with an on-chip charge pump with an architecture proposed in this paper.

Ultra Low Power 6T SRAM Cell Designed on 65nm Low Power Technology Platform Suitable for High Temperature Applications

Cell leakage (Istby) reduction of ultra low power (ULP) SRAM with conventional 6T configuration on 65nm low power (LP) technology platform is studied in the paper. Istby components are analyzed and optimized for the leakage reduction by adopting no sleep transistor or other leakage suppression schemes. Gate oxide of cell transistor is grown thicker compared to 65nm LP process to fully suppress the gate oxide leakage contribution. Sub-threshold leakage of the cell transistors are much decreased to lower down both the total Istby and its temperature sensitivity. The 16M ULP SRAM featuring a 0.525um2 bit cell size with the proposed technique shows Istby as low as 1.2pA/bit at 1.2V under room temperature and 3.1pA/bit at 85℃. The voltage data retention (VDR) of the ULP SRAM is shown to be 0.7V indicating the feasibility of Istby further reduction by applying low Vdd under stand by mode. Moreover, the ULP process is fully compatible with logic process flow, by adopting several more masks, the above mentioned SRAM can be embedded into standard CMOS flow easily.