Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Shikha Panwar,Aatreya Vivek Madgula,Mayuresh Piske

doi:10.1155/2014/380362

Shikha Panwar, Aatreya Vivek Madgula + Show 1 more

Open Access

https://doi.org/10.1155/2014/380362

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Journal: VLSI Design	Publication Date: Jul 15, 2014
Citations: 10	License type: CC BY 3.0

Affiliation: Vellore Institute of Technology University

Abstract

This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

Highlights

As we move on to finer MOSFET technologies, transistor delay has decreased remarkably which helped in achieving higher performance in CMOS VLSI processors
In drain gating technique [10] shown in Figure 1(a), two sleep transistors are added between the pull-up network (PUN) and pull-down network (PDN)
In drain-header and power-footer gating (DHPF), a PMOS sleep switch is inserted between PUN and output node and an NMOS sleep switch is inserted between the PDN and ground rail

Summary

Introduction

As we move on to finer MOSFET technologies, transistor delay has decreased remarkably which helped in achieving higher performance in CMOS VLSI processors. Power gating normally makes use of sleep transistors that are connected either between the power supply and the pull-up network (PUN) or between the pull-down network (PDN) and ground. An additional sleep transistor is connected in parallel with the transistor stack This reduces the leakage current but at the same time delay in the circuit is increased. In the same time GALEOR technique makes use of gated leakage transistors (GLTs) Both LCTs and GLTs reduce leakage by increasing the resistance between supply voltage and ground. Simulation results taking NAND gate, 1-bit full adder, and 8-bit RCA (Ripple carry adder) as test bench circuits are enumerated in Section 4 and Section 5 provides the final conclusion

Drain Gating Technique and Its Variant Circuits

The Proposed High Speed Circuit Techniques

Simulations and Results

Conclusions