Optimized design of MOS capacitors in standard CMOS technology and evaluation of their Equivalent Series Resistance for power applications

Abstract

An analytical study of the MOSFET-based capacitor is presented. This highly dense capacitive structure, suited to integrated circuits, is studied specifically for power applications by providing design guidelines for achieving minimum equivalent series resistance (ESR). The work includes layout strategies in standard digital CMOS technologies to provide optimal ESR, a design procedure for a target impedance at a given frequency, as well as a performance comparison with other on-chip capacitive structures such as poly-poly and metal-metal capacitors. The results are applicable for on-chip power circuits such as output filter stages in future integrated switching power converters, switched capacitor power converters, or decoupling circuits in high-performance on-chip power distributing networks.