Capacitor Size Research Articles

A Novel Approach Based on Honey Badger Algorithm for Optimal Allocation of Multiple DG and Capacitor in Radial Distribution Networks Considering Power Loss Sensitivity

Recently, the integration of distributed generators (DGs) in radial distribution systems (RDS) has been widely evolving due to its sustainability and lack of pollution. This study presents an efficient optimization technique named the honey badger algorithm (HBA) for specifying the optimum size and location of capacitors and different types of DGs to minimize the total active power loss of the network. The Combined Power Loss Sensitivity (CPLS) factor is deployed with the HBA to accelerate the estimation process by specifying the candidate buses for optimal placement of DGs and capacitors in RDS. The performance of the optimization algorithm is demonstrated through the application to the IEEE 69-bus standard RDS with different scenarios: DG Type-I, DG Type-III, and capacitor banks (CBs). Furthermore, the effects of simultaneously integrating single and multiple DG Type-I with DG Type-III are illustrated. The results obtained revealed the effectiveness of the HBA for optimizing the size and location of single and multiple DGs and CBs with a considerable decline in the system’s real power losses. Additionally, the results have been compared with those obtained by other known algorithms.

Finding Optimal Solutions for the Placement of Reactive and Active Power Generation Components in Distribution Networks Using a High-Performance Metaheuristic Algorithm

This paper proposes a modified slime mold algorithm (MSMA) for finding optimal site and size of both photovoltaic generators (PGs) and shunt capacitors (SCs) in radial distribution power systems (RDPSs). The most suitable site together with the most effective size of PGs and SCs can reduce currents of conductors effectively, resulting in the significant reduction of active power loss on all conductors. MSMA and two other applied algorithms, slime mold algorithm (SMA) and equilibrium optimizer (EO), are implemented for three study cases of IEEE 33, 69, and 85 RDPSs including Case (1) place only PGs with both active and reactive power generations; Case (2) place both SCs and PGs with only active power generation; and Case (3) place both SCs and PGs with both active and reactive power generations. Comparisons with SMA and EO, MSMA can reach either the same loss or much smaller loss for study cases. Furthermore, MSMA also outperforms other previously published methods for the three study cases, and it can reach significantly smaller loss for the three cases by 1.5%, 30.55%, and 19.64% for system 1, 7.59%, 0.26%, and 0.32% for system 2, and 7.51%, 34.2%, and 22.65% for system 3. As comparing the loss among three study cases obtained by MSMA, Case 3 can reach less loss than Case 1 and Case 2 by 11.71% and 11.64% for system 1, 26.27% and 26.13% for system 2, and the same 26.6% for system 3. Thus, it is recommended that MSMA is the most effective algorithm and the placement of both SCs and PGs with active and reactive power generations is the most optimal.

Optimal sizing and placement of shunt capacitors on the distribution system using Whale Optimization Algorithm

This paper aims at power loss minimization and reduction of cost due to losses in the distribution network as well as improvement of the network voltage stability and profile via optimal shunt capacitor allocation. The optimal shunt capacitor allocation was obtained using Whale Optimization Algorithm considering technical (real power loss and VSI) and economic objective functions as sub-optimal allocation may result in undesired effects on the network. The obtained optimal sizes of the shunt capacitors were placed on the obtained location of the distribution networks to ascertain the behavior of the networks before and after their placements taking power loss, cost due to losses, and voltage stability index as the performance metrics. A comparison of these performance metrics under four cases, namely base case (case one), installation of one SC (case two), installation of two SCs (case three), and installation of three SCs (case four) were demonstrated using standard IEEE 33-bus and Dada 46-bus distribution networks. The results gave a percentage loss reduction of 33.74% with 27.60% annual net saving for the IEEE 33-bus network and 22.24% loss reduction with 25.60% annual net saving for the Dada 46-bus network. Hence, reduction in the total power losses and costs. Also, the voltage profile and voltage stability index were significantly improved.

Wide-Output Range Power Processing Unit for 6-kW Hall Thruster

The Japan Aerospace Exploration Agency (JAXA) has developed a power processing unit (PPU) for a 6 kW Hall thruster system. The PPU is a candidate for future mission applications, such as all-electric satellites, exploration vehicles, and orbital transfer services. The PPU has to be small and still provide a wide output range of outputs, consider the in orbit and launch environments, and manage any instability in the Hall thruster's discharge. Specifically, the four converters that make up the anode power supply of the PPU is digitally controlled to reduce the size of the control circuit. It must operate stably despite small output capacitors and long dead times. This article clarifies the design criteria for the power supply, focusing on the size of capacitors and the PI control parameters to solve these problems. The result is a compact, high-performance PPU for the 6 kW Hall thruster. The power supply meets stringent design criteria and operates the thruster stably with an output voltage that can be varied between 200 and 730 V, provide a maximum power of 5.9 kW, and offer a maximum efficiency of 96.1% in the coupling test for the 6 kW Hall thruster. The proposed PPU, including the anode power supply, achieves a power density of 0.3 kW/kg, significantly higher than that of comparable PPUs.

Modeling of Non-Characteristic Third Harmonics Produced by Voltage Source Converter under Unbalanced Condition

A three-phase three-wire voltage source converter (VSC) can produce third harmonics when it is operated under an unbalanced condition. It is essential to understand the mechanism of the production of this third harmonic and to assess its impact on power systems. Therefore, this paper presents an analytical model of the VSC under the unbalanced condition through mathematical derivations, and the final model is a coupled Thevenin circuit. The proposed model allows for direct computation of the non-characteristic third harmonics through harmonic power flow studies. The results show that VSC under unbalanced conditions emits both positive-sequence and negative-sequence third harmonics, and that the positive-sequence third harmonic is much larger than the negative-sequence third harmonic. It also shows that the unbalanced level and the size of the dc-link capacitor are critical to the level of non-characteristic third harmonics. The correctness of the proposed model and its application on noncharacteristic third harmonic evaluations have been verified using EMT simulations.

Current Ripple Reduction Method in a Three-Phase Diode Rectifier With an Instantaneous Reactive Power Compensator

This article discussesthe control method for an ac/dc rectifier system consisting of a three-phase diode rectifier, a buck converter, and an instantaneous reactive power compensator (IRPC). The IRPC makes the grid current sinusoidal by controlling only the instantaneous reactive power. Thus, it is possible to reduce the size of the dc capacitors and ac inductors. This article analyzes the overlap in the rectifier, derives the suitable gain in the damping control, and proposes a modified control method for the IRPC to reduce the current ripple. A 4.5-kW laboratory setup was assembled and examined to verify the theory developed in this article. As a result, the modified control method effectively suppresses the spike current around the overlap duration and damps the overshoot/ringing caused by the resonance. The proposed ac/dc rectifier exhibits an improved power conversion efficiency of 98.2%.

Heuristic Optimization Approaches for Capacitor Sizing and Placement: A Case Study in Kazakhstan

Two methods for estimating the near-optimal positions and sizes of capacitors in radial distribution networks are presented. The first model assumes fixed-size capacitors, while the second model assumes controllable variable-size capacitors by changing the tap positions. In the second model, we limit the number of changes in capacitor size. In both approaches, the models consider many load scenarios and aim to obtain better voltage profiles by minimizing voltage deviations and active power losses. We use two recently developed heuristic algorithms called Salp Swarm Optimization algorithm (SSA) and Dragonfly algorithm (DA) to solve the proposed optimization models. We performed numerical simulations using data by modifying an actual distribution network in Almaty, Kazakhstan. To mimic various load scenarios, we start with the baseline load values and produce random variations. For the first model, the optimization algorithms identify the near-optimal positioning and sizes of fixed-size capacitors. Since the second model assumes variable-size capacitors, the algorithms also decide the tap positions for this case. Comparative analysis of the heuristic algorithms shows that the DA and SSA algorithms give similar results in solving the two optimization models: the former gives a slightly better voltage profile and lower active power losses.

Downlink Performance Modeling and Evaluation of Batteryless Low Power BLE Node.

Deploying low maintenance and long-life systems is an important requirement of emerging commercial Internet of Things (IoT) solutions. Such systems can be envisioned in which the connected devices are powered by energy harvested from ambient sources and stored in long-lifetime capacitors rather than short-lived and polluting batteries. However, due to the unpredictable nature of ambient energy harvesting, such batteryless IoT devices might not always have enough energy to initiate communication. The Bluetooth Low Energy (BLE) specification defines support for Low Power Nodes (LPNs) using the friendship feature, where the LPN is associated with a neighbouring friend node (FN). The LPN can receive downlink (DL) data and remain connected to the network via the FN that buffers the LPN’s incoming packets while allowing the LPN to save energy by sleeping or turning itself off. This novel BLE feature makes the LPN highly suitable to support the connection of batteryless ambiently-powered IoT devices. While the LPN can decide when to transmit uplink (UL) packets and does not depend on the FN to receive downlink (DL) data, the LPN needs to poll its FN to receive the buffered packets. However, the DL packet latency increases with this process due to the buffering time at the FN. Therefore, in this work, we present an analytical model to characterize the performance as a function of DL data latency and packet delivery ratio (PDR) of a batteryless LPN powered by different harvesting powers and capacitor sizes. This would help to optimally choose the correct configuration of the batteryless LPN for its network deployment. We also compare the analytical model and simulation results, showing consistency with an average error of 2.23% for DL data latency and 0.09% for the PDR.

Design and first implementation of wireless square-shaped transmission line resonators in 1H MRI for small animal studies

This work is dedicated to the development of a novel design for wireless transmission line resonators (TLRs). The TLRs are often considered as circular-shaped coils made up of two conductive circuits separated by a dielectric layer. We propose a square-shaped TLR design, wherein the coil has two square turns with two symmetrical gaps on each of the conductive layers, and the latter are rotated relative to each other by 90°. The calculation error of the resonant frequency of the square-shaped TLRs is no more than ∼3% of the measured value. The effectiveness of the square-shaped TLR design was evaluated in comparative 1H MRI studies to conventional wireless square loop of the same resonant frequency and with the same-sized inner square of the TLR. The Bruker birdcage was used as a transceiver and as inductively coupled with the wireless coils. We found that the performance of the square-shaped TLR and the square loop is comparable, but the B1+-field generated by the TLR has a wider distribution profile. It was reflected in rat brain studies, when some structures of rat head were not captured by the square loop. Comparative experiments with a standard circular-shaped TLR showed that a signal is predominantly concentrated inside the inner turn of the TLRs. The proposed TLR design can be a promising path to be explored, especially for scanning small objects of study, when the scan area is comparable to the size of the rigid lumped capacitors.

Batteryless Bluetooth Low Energy Prototype With Energy-Aware Bidirectional Communication Powered by Ambient Light

With the emerging deployment of Internet of Things devices, the industry is moving toward batteryless, maintenance-free, and sustainable solutions. Energy harvesting from ambient sources becomes crucial to support the uninterrupted execution of such applications. We choose the Bluetooth Low Energy (BLE) mesh network to analyze a batteryless node using the BLE Low power node (LPN) feature. We develop a prototype using a mini photovoltaic solar panel for indoor light harvesting using sunlight or a light bulb to power the BLE LPN. Due to the unpredictability of energy harvesting and the use of a small capacitor instead of a battery, the BLE LPN’s power can become intermittent. This causes the device to frequently switch between the ON and OFF states as it is unaware of its available energy while trying to perform scheduled tasks. In contrast, an energy-aware LPN can try to avoid the OFF state. With the knowledge of the capacitor voltage, it can proactively delay the execution of upcoming sensing or communication tasks and provide some time to recharge the capacitor while consuming a minimum amount of energy by switching itself to the SLEEP state. This article presents the developed prototype and evaluates an energy-unaware and -aware batteryless BLE LPN communicating uni-directional downlink only or bi-directional for different capacitor sizes at different light-harvesting powers. The experimental results conclude that the energy-aware batteryless LPN performs better for both uni- and bi-directional communication with improved DL data latency up to 74% and avoiding restarts.

Three‐stage CMOSamplifier: Frequency compensated using fully differential block

AbstractThe advancement of CMOS technology limits designers' options for multi‐stage configurations as a promising alternative to cascade structures. The main issue of designing multi‐stage amplifiers is frequency compensation since cascade structures are volatile. An efficient three‐stage amplifier, which is frequency compensated using a fully differential block, is proposed in this work. The differential block enhances the Miller effect to reduce the size of compensation capacitors, and this leads to less die occupation. The compensation network shares the differential block between two Miller loops while two Miller capacitors at the outputs of the differential block cause pole‐zero cancelation to increase operating frequency range. The proposed structure is modeled by a linear transfer function and simulated via HSPICE software using CMOS library. Simulation results indicate excellent performance and acceptable robustness against parameter mismatches and probable fabrication errors. According to the simulations, the proposed amplifier has a DC gain of , a gain‐bandwidth product of , a phase margin of , and a power dissipation of . The high performance of the proposed three‐stage amplifier with an enhanced figure of merit makes it a perfect alternative to the amplifiers based on the conventional reverse nested Miller compensation.

Optimal Placement of Capacitors in Radial Distribution Grids via Enhanced Modified Particle Swarm Optimization

This paper presents the integration of shunt capacitors in the radial distribution grids (RDG) with constant and time-varying load consideration for the reduction of power losses and total annual cost, which turns to enhance the voltage profile and annual net savings. To gather the stated goals, three objective functions are formulated with system constraints. To solve this identified problem, a novel optimization technique based on the modification of particle swarm optimization is proposed. The solution methodology is divided into two phases. In phase one, potential candidate buses are nominated using the loss sensitivity factor method and in phase two the proposed technique first selects the optimal buses for the capacitor placement among the potential buses then it decides the optimal sizing of the capacitors as well. To demonstrate the performance in terms of efficiency and strength, the proposed technique is tested on IEEE 15, 33, and 69 bus system for the optimal placement and sizing of capacitors (OPSC) problem. The results are achieved in terms of annual net savings for 15 bus (47.66%case−1, 32.76%case−2, 26.46%case−3), 33 bus (33.09% case−1, 27.06%case−2, 24.15%case−3), and 69 bus (34.51% case−1, 29.43%case−2, 25.83%case−3) which are comparable to other state of the art methods, and it also indicates the success of the proposed technique.

A 14-bit 40-MS/s Split-DAC based SAR ADC in 65 nm CMOS

A 14-bit 40 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is designed in this paper. The prototype was designed in CMOS 65-nm technology. To reduce the power dissipation, dual power supply has been used. Supply voltage for the analog blocks is 3.3 V, while digital block is powered by a 1.2-V supply. Sizes of capacitors in DAC arrays are decided mainly by the kT/C noise, matching requirement, chip area and consumed power. In this design, the sub-radix-2 redundant structure is employed to achieve compromise among these aspects. An on-chip LDO is also integrated in the proposed ADC to eliminate the incomplete DAC settling. The supply noise can be also suppressed by the adopted LDO due to its excellent PSRR performance. In addition, top-plate sampling is utilized to ensure the common-mode voltage of the DAC outputs is maintained, thus reducing the difficulty in the design of the comparator. The post-layout simulation results show that the ADC draws 20.9 mW with Nyquist input at 40 MS/s. With calibration, the SNDR and SFDR of the ADC achieve 84.9 dB and 95.4 dB. The active area of the ADC is 540 × 500 μm2.

Local-Oxide-Thinning-Induced Deep Depletion Phenomenon in MOS Capacitors

The influence of local oxide thinning (LOT) spots on the electrostatics of MOS capacitors was studied in this work. The capacitors are found to suffer from severe deep depletion (DD) above threshold once LOT spots that cause significant gate leakage are introduced, making them inapplicable for MOSFETs. With the help of simulation, we proposed the presence of a lateral electric field at the spot edge, which effectively drifts inversion charge toward the spot from its exterior, leading to severe depletion of inversion charge underneath the entire gate area. Capacitor size, spot size and spot thickness effects on the DD behavior were also investigated. This work demonstrates the high influence of LOT spots on device operations, as well as affirming the importance of oxide structural defect control.

Operating Limits for Low-Capacitance Cascaded H-Bridge Static Compensators

The cascaded H-bridge (CHB) low-capacitance static compensator (LC-StatCom) has a limited inductive region compared to a conventional StatCom, both in balanced and unbalanced conditions, due to the inherent large oscillations on the capacitor voltages. This article presents a detailed analysis of the viable operating region in these converters that takes into account the inherent large oscillations. The analysis facilitates sizing of the dc-link capacitors to ensure that the StatCom is able to inject a given range of positive- and negative-sequence current. Though the analysis is generic and applicable to the CHB StatComs with relatively large capacitance values, it is more relevant in the LC-StatComs. In addition, the article derives reference steady-state signals that can be used as feedforward terms in LC-StatCom control loops to enhance the control performance. The article presents simulation and experimental results, in balanced and unbalanced conditions to corroborate the proposed analysis.

Discontinuous Modulation of a Cascaded H-Bridge Low-Capacitance StatCom

This article presents a discontinuous modulation (DM) strategy for static compensators (StatComs) based on a cascaded H-bridge (CHB) converter with a star configuration. The proposed DM strategy considers the capacitor voltage oscillations at twice the fundamental frequency and the effect of zero-sequence voltage injection on the capacitor voltages. Considering these effects is especially important in CHB-StatComs with large capacitor voltage ripples (low-capacitance StatComs), where the assumption of a constant dc-link voltage, which is the basis of conventional DM strategies, does not apply. This article also describes a coherent set of steady-state waveforms for CHB-StatComs under DM. In addition to the well-known benefit of reducing the switching losses, the proposed DM also reduces the dc-link capacitors size and extends the operating range. The viability of the proposed DM strategy is verified experimentally on a small-scale prototype. In addition, simulation results are obtained using a real-scale system to study feasibility of the DM under unbalanced conditions.

Efficient Hybrid Algorithm Solution for Optimal Reactive Power Flow Using the Sensitive Bus Approach

This paper presents the design and application of an efficient hybrid algorithm for solving the Optimal Reactive Power Flow (ORPF) problem. The ORPF is formulated as a nonlinear constrained optimization problem where the active power losses must be minimized. The proposed approach is based on the hybridization of Particle Swarm Optimization (PSO) and Tabu-Search (TS) technique. The proposed PSO-TS approach is used to find the settings of the control variables (i.e. generation bus voltages, transformer taps, and shunt capacitor sizes) which minimize transmission active power losses. The bus locations of the shunt capacitors are identified according to sensitive buses. To show the effectiveness of the proposed method, it is applied to the IEEE 30 bus benchmark test system and is compared with PSO and TS without hybridization, along with some other published approaches. The obtained results reveal the effectiveness of the proposed method in dealing with the highly nonlinear constrained nature of the ORPF problem.

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors.

Herein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). The proposed approach tackles the drawback of the previous active noise shaping (increased power and extra noise) and passive noise shaping (limited noise suppression and signal loss). Both noise shaping and gain multiplication are realized on-chip in an energy-efficient manner without an opamp. This approach uses only capacitors and switches in the finite impulse response (FIR) and infinite impulse response (IIR) filters. A comparator suppressing kickback noise is presented to handle the tradeoff between noise suppression and the filter capacitor size. The energy-efficient merged-capacitor switching (MCS) technique is effectively combined with rail-to-rail swing comparator and thermometer-coded capacitor array, which reduces the settling error in the digital to analog converter (DAC). The process-induced mismatch effect in the capacitive DAC is investigated using a behavioral model of the ADC. Additionally, we propose dynamic element matching (DEM) for the thermometer-coded capacitor array. The ADC is fabricated using a 0.18 μm CMOS process in an area of 0.26 mm2. Consuming 4.1 μW, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 66.5 dB and a spurious-free dynamic range (SFDR) of 79.1 dB. The figure-of-merit (FoM) of the ADC is 11.8 fJ/conversion-step.

An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

This paper presents an energy efficient architecture for successive approximation register (SAR) analog to digital converter (ADC). SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed. However, conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits. The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes. The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor (CMOS) library using Cadence Virtuoso design tool. Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3% compared with conventional SAR ADC, compared with the SAR ADC with split capacitor, and compared with the resistor and capacitor (R&C) Hybrid SAR ADC. The ADC achieves an effective number of bits (ENOB) of bits and consumes at sampling rate of , offering an energy consumption of per conversion step. The proposed SAR ADC offers 95.5% reduction in chip core area compared to conventional architecture, while occupying an active area of .

Power loss minimization and voltage profile improvement on electrical power distribution systems using optimal capacitor placement and sizing

Distribution system operators are having difficulties maintaining a correct voltage profile across its network. As the standard of living of its customers increases, suppressed loads tend to come up and this in turn would require and increased demand in power supply. The increase in power demand and high load density at distribution ends have been seen to have key consequences of increasing the power loss and reducing the voltage profile in power systems, which seriously jeopardizes the ability of radial distribution networks to faithfully account for the power received from transmission stations. This work is aimed at improving the power quality that gets to the end users. Shunt capacitors have been suggested to be a suitable solution to this problem as they supply the reactive power needed for compensation. As a result, the optimum placement and size of these shunt capacitors have received a great deal of attention. Despite its efficacy, meta-heuristic algorithms are seldom utilized in the Nigerian RDS (radial distribution system), since most published research instead uses analytical and numerical programming methods. As a result, this research explains how to use a Hybrid Solution (HS) of Particle Swarm Optimization (PSO and GA) to identify and size shunt capacitors for real-time power loss reduction on an 11-kV distribution feeder. The backward-forward sweep load flow method with Loss Sensitivity Factor (LSF) is used to identify suitable buses for shunt capacitor installation, and the HS algorithm is then used to estimate the optimum size. This method was discovered to decrease the system's real power loss by 54.88% while raising the minimum bus voltage magnitude to the acceptable limit and thus improving the minimum system Voltage Stability Index (VSI). Based on these findings, the suggested technique is regarded as a viable way for placement and determining the size of shunt capacitors in a real-world Radial Distribution System. The numerical results shows that the approach has a high capability of improving the voltage profile of the distribution network, leading to an improved system power quality, minimize the system losses, correct the power factor, and maximize the net savings. The numerical results were gotten by using MATLAB package.