A 14-bit 40-MS/s Split-DAC based SAR ADC in 65 nm CMOS

Abstract

A 14-bit 40 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is designed in this paper. The prototype was designed in CMOS 65-nm technology. To reduce the power dissipation, dual power supply has been used. Supply voltage for the analog blocks is 3.3 V, while digital block is powered by a 1.2-V supply. Sizes of capacitors in DAC arrays are decided mainly by the kT/C noise, matching requirement, chip area and consumed power. In this design, the sub-radix-2 redundant structure is employed to achieve compromise among these aspects. An on-chip LDO is also integrated in the proposed ADC to eliminate the incomplete DAC settling. The supply noise can be also suppressed by the adopted LDO due to its excellent PSRR performance. In addition, top-plate sampling is utilized to ensure the common-mode voltage of the DAC outputs is maintained, thus reducing the difficulty in the design of the comparator. The post-layout simulation results show that the ADC draws 20.9 mW with Nyquist input at 40 MS/s. With calibration, the SNDR and SFDR of the ADC achieve 84.9 dB and 95.4 dB. The active area of the ADC is 540 × 500 μm2.