A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Min-Jae Seo

doi:10.3390/electronics10040421

Abstract

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

Highlights

High-resolution (>10 effective number of bits (ENOB) (Effective Number of Bits)) and high-speed (>150 MS/s) analog-to-digital converters (ADCs) with low power consumption have become an essential building block in modern wireless communication systems
The two sampled dual residues are interpolated by the I-SAR ADC during Φc2, while a new input is sampled on the 1st-stage SIG-CDAC
A prototype 12 bit 200 MS/s pipelined-SAR ADC with the proposed single-amplifier dual-residue architecture and I-SAR ADC was implemented in 40 nm CMOS technology

Summary

Introduction

High-resolution (>10 ENOB (Effective Number of Bits)) and high-speed (>150 MS/s) analog-to-digital converters (ADCs) with low power consumption have become an essential building block in modern wireless communication systems. Among the several architectural approaches, the SAR-assisted pipeline configurations have been proven a promising high-speed high-resolution ADC structure with excellent energy efficiency [6–17]. Even though the dynamic amplifiers recently reported in [6,7] showed remarkable power efficiency and speed, the calibration circuitry for accurate residue gain is an unavoidable overhead. Because the conversion scheme uses the ratio of the two residues to find the LSB code, it is important that the two residues are amplified by the same gain value. This means that the relative gain value between the two RAs is more important than the absolute gain value.

Review of Dual-Residue Processing Concept

Proposed Architecture

Measurement Results and Discussion

Conclusions